Vinod K. Agarwal

A new procedure for weighted random built-in self-test

It is proposed that a pseudorandom sequence and a single weighted random sequence be used to implement built-in self-test (BIST) efficiently in a large integrated scan circuit which would otherwise need an excessive pseudorandom test length. A method of determining the weight set and the approximate pseudorandom and weighted random test lengths, based on fast fault simulation tools, is suggested. By modifying specific scan cells, the BIST hardware conditionally generates the weighted stream locally, at specific input sites. A weighted control signal is used to regulate the proportion of weighted and pseudorandom inputs. Apart from determining that, in the cases examined, one weight set was sufficient for a notable decrease in test time, it was also noticed that a very coarse weight set (i.e. restricting biases to 0, 0.25, 0.5, 0.75, and 1) provides acceptable results. Using finer resolution within the weight set usually results in a slightly higher coverage, but at the expense of a much higher area overhead.<<ETX>>

Serial interfacing for embedded-memory testing

A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable.<<ETX>>

Testing and diagnosis of interconnects using boundary scan architecture

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes.<<ETX>>

Implementing a Built-In Self-Test PLA Design

An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressed output data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint, and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and product terms, respectively). The article begins with a short review of existing design schemes.

Built-in self-diagnosis for repairable embedded RAMs

A method of built-in self-diagnosis (BISD) for repairable, embedded static RAMs (SRAMs) is presented. The BISD circuit, with self-repair, requires about 5% extra area in a 64-kb SRAM. The circuit contains a small reduced-instruction-set processor, which executes diagnosis algorithms stored in a ROM. These algorithms employ hybrid serial/parallel operations when external repair is available or modular operations when self-repair is required. The algorithms, hardware design, and design costs and tradeoffs are discussed.<<ETX>>

A diagnosis method using pseudo-random vectors without intermediate signatures

A diagnosis method is proposed which may be used to locate faults in circuits tested with random or pseudorandom test vectors. No intermediate signatures are involved, and the external hardware required is not complex. This proposed diagnosis scheme, called DAPPER, is applicable to multioutput combinational circuits. DAPPER classifies faults initially by their detection probability for coarse resolution, and secondly using their first failing pattern and a conventional signature for fine resolution. This method uses offline posttest simulation to isolate a single fault with only a fraction of the simulation that would ordinarily be required. Additionally, any failures within the test hardware itself may be diagnosed using the method.<<ETX>>

BIST of PCB interconnects using boundary-scan architecture

The issues of printed circuit board (PCB) interconnect testing are addressed in the context of boundary-scan architecture. Boundary-scan architecture is treated here as the framework for a PCB level built-in self-test (BIST). A novel BIST method is developed which utilizes various features of the architecture. Boundary-scan architecture is shown to have the capability to generate time-efficient test vector sets. Response compaction within the boundary-scan chain is introduced to reduce shift out time as well as to simplify detection and diagnosis. However, the proposed BIST schemes require some extensions of the standard boundary-scan cells, and the schemes can work only if every boundary-scan cell of every IC on the PCB has the proposed extensions. >

An iterative technique for calculating aliasing probability of linear feedback signature registers

An iterative technique for computing the exact probability of aliasing for any linear feedback signature register (i.e. characterized by any feedback polynomial, for any constant probability of error, and for any test length) is proposed. The technique is also applicable to a more general model of the aliasing problem wherein the probability of error may vary with each output bit. The complexity of the technique enables registers of lengths of interest in practice, e.g. 16, to be analyzed readily.<<ETX>>

Distributed diagnosis algorithms for regular interconnected structures

A distributed diagnosis algorithm to locate faulty processing elements in large-scale regular interconnected structures based on the concepts of system-level diagnosis is developed. This algorithm can either operate in a systolic manner or may be executed on a supervisory processor to locate the faulty processors. The computational complexity of the algorithm is linear when run on a supervisory processor and constant when run in parallel systolic manner. The implementation complexity and diagnosis capability of the algorithm are also analyzed without restricting the fault set size. The probability of correct diagnosis is shown to be very high even in the presence of large fault sets. >

Optimizing error masking in BIST by output data modification

The error masking in conventional built-in self-test schemes is known to be around 2−m when the output data is compacted in an m-bit multi-input linear feedback shift register. In the recent years, several schemes have been proposed which claim to reduce the error masking in a significant way while maintaining the need for a small overhead. In this paper, a completely new scheme for reducing error masking is proposed. Unlike the previous schemes in the literature, the new scheme is circuit-dependent and uses the concept of output data modification. This concept suggests modifying the original test output sequence before compaction, in order to obtain a new sequence with a reduced error masking probability. It is shown that the output data modification scheme provides a simple trade-off between the desired error masking which could run into (21thousands) and the area overhead needed (which would usually be equal to a 16 or 32 bit multi-input linear feedback shift register) for this masking. Finally, a formal proof is presented which establishes that despite circuit-dependency, the proposed scheme will on the average always lead to the desired error masking.