Vinu Vijay Kumar

Highly flexible multimode digital signal processing systems using adaptable components and controllers

Multimode systems have emerged as an area- and power-efficient platform for implementing multiple timewise mutually exclusive digital signal processing (DSP) applications in a single hardware space. This paper presents a design methodology for integrating flexible components and controllers into primarily fixed logic multimode DSP systems, thereby increasing their overall efficiency and implementation capabilities. The components are built using a technique called small-scale reconfigurability (SSR) that provides the necessary flexibility for both intermode and intramode reconfigurabilities, without the penalties associated with general-purpose reconfigurable logic. Using this methodology, area and power consumption are reduced beyond what is provided by current multimode systems, without sacrificing performance. The results show an average of 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and 68% reduction in the number of controller signals, with an average 38% increase in component utilization for a set of benchmark 32-bit DSP applications.

Designing, Scheduling, and Allocating Flexible Arithmetic Components

This paper introduces new scheduling and allocation algorithms for designing with hybrid arithmetic component libraries composed of both operation-specific components and flexible components capable of executing multiple operations. The flexible components are implemented primarily in fixedlogic with only small amounts of application-specific reconfigurability, which provides the flexibility needed without the negative area and performance penalties commonly associated with general-purpose reconfigurable arrays. Results obtained with hybrid library scheduling and allocation on a variety of digital signal processing (DSP) filters reveal that significant area savings are achieved.

Fine-grained self-healing hardware for large-scale autonomic systems

The hardware redundancy costs required for self-healing systems increase with system complexity, creating concerns about the cost-feasibility of large-scale autonomic systems. Redundancy costs can be minimized without reducing reliability by providing finest-grained fault recovery, but modern redundancy techniques are not effective for sub-component-level recovery. This paper introduces a design technique for low-cost, fine-grained self-healing hardware. Small amounts of reconfigurable logic are integrated within primarily fixed-logic circuits to provide heterogeneous redundancy for efficient fine-grained, self-contained fault detection, diagnosis, and recovery. When combined with traditional coarse-grained recovery techniques for larger failures, this technique enables large-scale self-healing systems with reduced redundancy costs.

Heterogeneous redundancy for fault and defect tolerance with complexity independent area overhead

The continuous increase in digital system complexity is raising the area cost of redundancy-based fault and defect tolerance. This paper introduces a technique for heterogeneous redundancy in control path and datapath circuitry that provides high reliability with area overhead that is independent of system complexity. Small amounts of circuit-specific reconfigurable logic are finely integrated with fixed-logic circuitry to provide fine-grained heterogeneous fault and defect tolerance. Results reveal that the technique is effective for a variety of circuits, providing high reliability with a constant magnitude area overhead that is independent of system complexity.

IC modeling for yield-aware design with variable defect rates

This paper introduces a modeling methodology that enables design tradeoffs to be performed between yield, throughput and area while targeting process technologies with variable defect rates. A combinatorial model is used to represent candidate circuits in the presence of burn-in component failures, and area and throughput rewards are used for evaluating the expected quality of the final implementation while taking yield issues into consideration. A case study on a benchmark FIR filter design reveals how the methodology can be incorporated into the system design process to evaluate numerous design options implemented on various semiconductor process technologies.

A Markov reward model for reliable synchronous dataflow system design

The design of quality digital systems depends on models that accurately evaluate various options in the design space against a set of prioritized metrics. While individual models for evaluating area, performance, reliability, power, etc. are well established, models combining multiple metrics are less mature. This paper introduces a formal methodology for comprehensively analyzing performance, area and reliability in the design of synchronous dataflow systems using a novel Markov Reward Model. A Markov chain system reliability model is constructed for various design options in the presence of possible component failures, and high-level synthesis techniques are used to associate performance and area rewards with each state in the chain. The cumulative reward for a chain is then used to evaluate the corresponding design option with respect to the metrics of interest. Application of the model to a benchmark DSP circuit provides insights into reliable synchronous dataflow system design.

Small-scale reconfigurability for improved performance and double-precision in graphics hardware

We explore the application of small-scale reconfigurability (SSR) to graphics hardware. SSR is an architectural technique wherein functionality common to multiple subunits is reused rather than replicated, yielding high-performance reconfigurable hardware with reduced area requirements (Vijay Kumar and Lach “Designing, scheduling, and allocating flexible arithmetic components”, in Proceedings of the International Conference on Field Programmable Logic and Applications, 2003). We show that SSR can be used effectively in programmable graphics architectures to allow double-precision computation without affecting the performance of single-precision calculations and to increase fragment shader performance with a minimal impact on chip area.

Application specific small-scale reconfigurability

Fixed logic circuit design and fabrication is the preferred implementation route for applications with exacting performance, area, and/or power requirements. However, the resulting fixed logic application-specific integrated circuits (ASICs) lack the flexibility to adapt to faults and other runtime events, to changing design specifications and process parameters, or for multi-function execution. Traditional approaches for achieving hardware flexibility with programmable processors or large-scale, general-purpose reconfigurable fabrics (e.g. field programmable gate arrays (FPGAs)) impose significant area, delay, and power penalties compared to fixed logic ASICs. Small-scale reconfigurability (SSR) is a new design technique that minimizes these penalties by finely integrating into a primarily fixed logic circuit only the amount of reconfigurable logic and interconnect that is required for a particular application, at a gate-level granularity. SSR circuits have the necessary flexibility with ASIC-like efficiency due to the fine integration and application-specific implementation. This dissertation introduces SSR and methodologies for applying SSR to the implementation of flexible systems for three major applications: flexible multi-mode system synthesis, low complexity fine-grained heterogeneous redundancy for online testing and fault tolerance, and yield- and reliability-aware flexible design. Results of applying SSR to these application areas reveal the efficacy of this technique in bridging the efficiency/flexibility gap between traditional fixed logic ASICs and general-purpose reconfigurable fabrics.