Virginie Nodjiadjim

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ges50-GHz- clock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD- HBT equations. These large signal models have allowed the design of 50-GHz clocked 50 G Decision and 100 G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

Serial 100 Gb/s connectivity based on polymer photonics and InP-DHBT electronics.

We demonstrate the first integrated transmitter for serial 100 Gb/s NRZ-OOK modulation in datacom and telecom applications. The transmitter relies on the use of an electro-optic polymer modulator and the hybrid integration of an InP laser diode and InP-DHBT electronics with the polymer board. Evaluation is made at 80 and 100 Gb/s through eye-diagrams and BER measurements using a receiver module that integrates a pin-photodiode and an electrical 1:2 demultiplexer. Error-free performance is confirmed both at 80 and 100 Gb/s revealing the viability of the approach and the potential of the technology.

A Large-Swing 112-Gb/s Selector-Driver Based on a Differential Distributed Amplifier in InP DHBT Technology

We report a 2:1 selector-driver based on a differential distributed amplifier realized in a 0.7-μ m indium phosphide double heterojunction bipolar transistor technology. From transistors reaching fT/fmax of 320/380 GHz and a breakdown voltage (BVCEO) of 4.5 V, the selector-driver provides a differential eye amplitude of up to 6.2 and 5.9 VPP at up to 100 and 112 Gb/s, respectively, for a power consumption of 3.8 W, achieving a record swing-speed product of 620 and 660 VGb/s, respectively.

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

The reliability of InP/GaAsSb/InP DHBTs designed for very high-speed ICs applications is studied after storage accelerated aging tests performed up to 2000 hours at ambient temperatures of 180, 210 and 240°C. The HiCuM model was used for modelling DC electrical characteristics measured during aging tests. The signature of the major degradation mechanism points out an evolution of the emitter access resistance. The failure mechanism is related to the Au and/or Ti diffusion into InGaAs emitter contact layer. However, the maximum current gain decrease is lower than 7 % after 2000 hours at 240°C. This shows the robustness of the InP/GaAsSb/InP DHBT under test.

Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management

More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.

Multi-100 GbE and 400 GbE Interfaces for Intra-Data Center Networks Based on Arrayed Transceivers With Serial 100 Gb/s Operation

We demonstrate a 2 × 100 Gb/s transmitter and a 4 × 100 Gb/s receiver as the key components for multi-100-GbE and 400-GbE optical interfaces in future intradata center networks. Compared to other approaches, the two devices can provide significant advantages in terms of number of components, simplicity, footprint, and cost, as they are capable of serial operation with nonreturn-to-zero on-off keying format directly at 100 Gb/s. The transmitter is based on the monolithic integration of a multimode interference coupler with two Mach-Zehnder modulators on an electro-optic polymer chip, and the hybrid integration of this chip with an InP laser diode and two multiplexing and driving circuits. The receiver on the other hand is based on the hybrid integration of a quad array of InP photodiodes with two demultiplexing circuits. Combining the two devices, we evaluate their transmission performance over standard single-mode fibers without dispersion compensation and achieve a BER of 10-10 after 1000 m and a BER below 10-8 after 1625 m at 2 × 80 Gb/s, as well as a BER below 10-7 after 1000 m at 2 × 100 Gb/s. Future plans including the development of tunable 100 GbE interfaces for optical circuit-switched domains inside data center networks are also discussed.

\(2 \times 100\) -Gb/s NRZ-OOK Integrated Transmitter for Intradata Center Connectivity

We demonstrate an integrated transmitter that can generate two 100-Gb/s optical channels with simple nonreturn-to-zero-ON-OFF keying format. The transmitter is based on the combination of an ultrafast electro-optic polymer platform for the photonic integration and the optical modulation with ultrafast InP-double heterojunction bipolar transistor electronics for the multiplexing and the amplification of the 100-Gb/s driving signals. Through error-free transmission of 2 × 80-Gb/s signals over 1 km of SMF and transmission of 2 × 100-Gb/s signals over 500 m of single-mode fiber with error performance way below the forward error correction limit, we reveal the potential of the approach for parallel 100-GbE optical interfaces in small footprint transceivers for intradata center networks.

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

Abstract The reliability of InP/InGaAs DHBT under high collector current densities and low junction temperatures is analyzed and modeled. From the Gummel characteristics, we observe several types of device degradation, resulting from the long term changes of base and collector current in both lower and higher base–emitter voltage ranges which impacts the reduction of DC current gain. In this paper, we investigate the underlying physical mechanism of base and collector current degradation with the help of TCAD device simulation. We chose the HICUM model level2 for the modeling purpose to evaluate the drift of model parameters according to stress time. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.

InP Double Heterojunction Bipolar Transistor for broadband terahertz detection and imaging systems

This paper presents terahertz detectors based on high performance 0.7-μm InP double heterojunction bipolar transistor (DHBT) technology and reports on the analysis of their voltage responsivity over a wide frequency range of the incoming terahertz radiation. The detectors operated without any spatial antennas to couple terahertz radiation to the device and have been characterized in the 0.25 - 3.1 THz range with the responsivities (normalized to 1 W radiant power) of 5 V/W and 200 μV/W measured at 0.35 THz and 3.11 THz, respectively. The InP DHBTs also performed as the imaging single-pixels at room temperature in the raster scanned transmission mode. A set of the sub-terahertz images of plant leaves suggest potential utility of InP DHBT detectors for terahertz imaging dedicated to non-invasive testing of plants.

Advancements on reliability-aware analog circuit design

This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature stress it suffers which results in (slowly) varying model parameters over time. Due to its straightforward implementation in commercial Computer Aided Design (CAD) flows, this method allows designers creating reliability-aware circuit architectures at an early stage of the design procedure, well before real circuits are actually fabricated. Application examples and results are presented for an InP/InGaAs DHBT process, but the universality of the method makes it suitable also for silicon based technologies such as CMOS and (SiGe) BiCMOS.