Vitaly Bondarenko

Nanostructures formed by displacement of porous silicon with copper: from nanoparticles to porous membranes

The application of porous silicon as a template for the fabrication of nanosized copper objects is reported. Three different types of nanostructures were formed by displacement deposition of copper on porous silicon from hydrofluoric acid-based solutions of copper sulphate: (1) copper nanoparticles, (2) quasi-continuous copper films, and (3) free porous copper membranes. Managing the parameters of porous silicon (pore sizes, porosity), deposition time, and wettability of the copper sulphate solution has allowed to achieve such variety of the copper structures. Elemental and structural analyses of the obtained structures are presented. Young modulus measurements of the porous copper membrane have been carried out and its modest activity in surface enhanced Raman spectroscopy is declared.

Comparative study of initial stages of copper immersion deposition on bulk and porous silicon

Initial stages of Cu immersion deposition in the presence of hydrofluoric acid on bulk and porous silicon were studied. Cu was found to deposit both on bulk and porous silicon as a layer of nanoparticles which grew according to the Volmer-Weber mechanism. It was revealed that at the initial stages of immersion deposition, Cu nanoparticles consisted of crystals with a maximum size of 10 nm and inherited the orientation of the original silicon substrate. Deposited Cu nanoparticles were found to be partially oxidized to Cu2O while CuO was not detected for all samples. In contrast to porous silicon, the crystal orientation of the original silicon substrate significantly affected the sizes, density, and oxidation level of Cu nanoparticles deposited on bulk silicon.

Transfer layer technology for the packaging of high power modules

Most power electronic modules are specifically designed for the customer and this entails intense labour during the production phase. The monolithic integration for power electronic devices in the form of power IC has not proven to be efficient, neither from a technical, nor from an economic point of view. In a typical high power module the power devices are assembled on a heatsink and, driver, sensor and protection circuits are mounted on separate PCBs assembled to the power devices. This results in low performance and high cost. Higher integrated power modules are produced assembling power devices in die format onto a DCB (Direct Copper Bonding) substrate and interconnect them by wire bonding technique [1]. The relative driver, sensor and protection circuits are surface mounted on a separate PCB assembled with the former.

Porous silicon technology, a breakthrough for silicon photonics: From packaging to monolithic integration

Low cost concept based on the porous silicon technology is shown to be well suitable for integrating monolithically the photonic devices on a standard silicon wafers by using localized SOI structures fabricated by electrochemical anodization of silicon wafers followed by thermal oxidation of porous silicon. The new approach consists in realizing buried localized porous oxidized silicon by exploiting two different routes: n- epi/n+/n- structures on p-type wafers and ion-implantation on standard CMOS/BiCMOS wafers. The peculiarities of the developed approach, including anodization and thermal oxidation regimes to form oxidized porous silicon regions with the required properties are presented. The advantages of the proposed approach in realizing the fiber-to-chip and power-over-fiber coupling are discussed.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

Electrochemically etched TSV for porous silicon interposer technologies

Silicon interposer technology offers System-In-Package (SiP) and System-On-Package (SoP) designers the unique possibility of achieving 3D integration without the need to implement Through-Silicon-Via (TSV) structures in active silicon, contributing to overall cost reduction of the final product. Silicon interposers require both horizontal and vertical interconnections, to redistribute the signals from the hosted chips. Vertical interconnections are achieved by TSV structures realized by Deep Reactive-Ion-Etching (DRIE) or LASER drilling processes. In this work is presented a lower cost alternative for realizing TSV on silicon wafers: electrochemical etching of silicon, forming vertical high aspect ratio macro-pores on the silicon wafer. The interposer itself is a macro-porous silicon layer, consisting of ordered, straight open pores at regular pitch. An optimized TSV fabrication process on low-cost (100)-oriented, p-type 10-20 Ωcm silicon wafers is presented. 100μm deep via with lateral diameter of 1.5μm and 2μm pitch have been achieved. In this work is reported the manufacture process, the achieved results.

High density compliant contacting technology for integrated high power modules in automotive applications

In this work it is described an high-density contacting technology that can replace wire bonding in power electronic applications, to overcome known limitation of bond wires liftoff occurring after several power cycles due to the difference in the coefficient of thermal expansion of silicon and aluminum. In the presented technology, MEMS (micro-electro-mechanics systems) micro-fabrication processes are used to realize contact structures that, pressed against the silicon dice, provide a reliable compliant contact. One advantage of this technology is that the contacts can be hosted on a printed circuit board that integrates the control circuitry for the power devices. This will reduce the footprint of power systems, like Integrated High Power Modules (IHPM). Reduced footprints are beneficial in applications where space is a concern, like the automotive industry. The description of the technological steps for building the contacting assembly is reported together with process conditions and electrical performances of two test structures.

Experimental study of the sensitivity of a porous silicon ring resonator sensor using continuous in-flow measurements

A highly sensitive photonic sensor based on a porous silicon ring resonator was developed and experimentally characterized. The photonic sensing structure was fabricated by exploiting a porous silicon double layer, where the top layer of a low porosity was used to form photonic elements by e-beam lithography and the bottom layer of a high porosity was used to confine light in the vertical direction. The sensing performance of the ring resonator sensor based on porous silicon was compared for the different resonances within the analyzed wavelength range both for transverse-electric and transverse-magnetic polarizations. We determined that a sensitivity up to 439 nm/RIU for low refractive index changes can be achieved depending on the optical field distribution given by each resonance/polarization.

ZnO Films and Crystals on Bulk Silicon and SOI Wafers: Formation, Properties and Applications

In present work the investigation of the electrochemical and chemical hydrothermal deposition processes of ZnO on silicon is presented. The influence of the electrochemical process parameters on the characteristics and morphology of the ZnO deposits is analyzed. Electrochemical deposition from non aqueous DMSO solutions on porous silicon buffer layer is also discussed. The details of the chemical hydrothermal deposition from the nitrate bath of high-quality ZnO crystals on silicon substrate are presented. It was shown that morphology and size of synthesized ZnO crystals depends on the temperature of the deposition bath. Differences between photoluminescence of electrochemically deposited ZnO thin films and hydrothermally synthesized crystals are shown. Electrochemically deposited ZnO films demonstrate defect-caused luminescence and hydrothermally grown ZnO crystals shows intensive exciton luminescence band in UV region. Hydrothermal deposition of high-quality ZnO crystals on the surface of electrochemically deposited ZnO seed layer with porous silicon buffer improves photoluminescence properties of the structure which is useful for optoelectronics applications. Possible applications of ZnO as gas sensors and photovoltaic devices are considered. Aspects of ZnO electrochemical deposition on bulk silicon and silicon-on-isolator wafers for integration purposes are discussed.

Visible photoluminescence of zinc oxide films electrochemically deposited on silicon substrates

Continuous crystalline films of zinc oxide (ZnO) with thicknesses of 6–10 μm were obtained by electrochemical deposition from aqueous zinc nitrate solutions on silicon substrates with a buffer nickel layer. X-ray diffraction measurements showed that the polycrystalline films possess a hexagonal crystal lattice with predominant (0002) orientation. The obtained ZnO films exhibit strong photoluminescence in the visible spectral range at room temperature.