Vlad P. Shmerko

Evolutionary multi-level network synthesis in given design style

This paper extends the technique of evolutionary network design. We study an evolutionary network design strategy from the position of design style. A hypothesis under investigation is that the uncertainty of a total search space (the space of all possible network solutions) through evolutionary network design is removed faster if this space is partitioned into subspaces. This idea has been realized through a parallel window-based scanning of these subspaces. Such a window is determined by the parameters of a multi-level network architecture in a given design style. Our approach allows to synthesize networks with more than two hundred quaternary gates. Moreover we show that information theoretical interpretation of the evolutionary process is useful, in particular in partitioning of network space and measuring of fitness function. The experimental data with 6-input quaternary and 11-inputs binary benchmarks demonstrate the efficiency of our program, EvoDesign, and an improvement against the recently obtained results.

Logic Design of NanoICS

PREFACE ACKNOWLEDGEMENTS INTRODUCTION Progress From Micro- to Nanoelectronics Logic Design in Spatial Dimensions Towards Computer-Aided Design of NanoICs Methodology Example: Hypercube Structure of Hierarchical FPGA Summary Problems Further Reading References NANOTECHNOLOGIES Nanotechnologies Nanoelectronic Devices Digital Nanoscale Circuits: Gates vs. Arrays Molecular Electronics Scaling and Fabrication Summary Problems Further Reading References BASICS OF LOGIC DESIGN IN NANOSPACE Graphs Data Structures for Switching Functions Sum-of-Products Expressions Shannon Decision Trees and Diagrams Reed-Muller Expressions Decision Trees and Diagrams Arithmetic Expressions Decision Trees and Diagrams Summary Problems Further Reading References WORD-LEVEL DATA STRUCTURES Word-level Data Structures Word-level Arithmetic Expressions Word-level Sum-of-Products Expressions Word-level Reed-Muller Expressions Summary Problems Further Reading References NANOSPACE AND HYPERCUBE-LIKE DATA STRUCTURES Spatial Structures Hypercube Data Structure Assembling of Hypercubes N-Hypercube Definition Degree of Freedom and Rotation Coordinate Description N-Hypercube Design for n > 3 Dimensions Embedding a Binary Decision Tree in N-Hypercube Assembling Spatial Topological Measurements Summary Problems Further Reading References NANODIMENSIONAL MULTILEVEL CIRCUITS Graph-Based Models in Logic Design of Multilevel Networks Library of N-Hypercubes for Elementary Logic Functions Hybrid Design Paradigm: N-Hypercube and DAG Manipulation of N-Hypercubes Numerical Evaluation of 3-D Structures Summary Further Reading References LINEAR WORD-LEVEL MODELS OF MULTILEVEL CIRCUITS Linear Expressions Linear Arithmetic Expressions Linear Arithmetic Expressions of Elementary Functions Linear Decision Diagrams Representation of a Circuit Level by Linear Expression Linear Decision Diagrams for Circuit Representation Technique for Manipulating the Coefficients Linear Word-level Sum-of-Products Expressions Linear Word-level Reed-Muller Expressions Summary Problems Further Reading References EVENT-DRIVEN ANALYSIS OF HYPERCUBE-LIKE TOPOLOGY Formal Definition of Change in a Binary System Computing Boolean Differences Models of Logic Networks in Terms of Change Matrix Models of Change Models of Directed Changes in Algebraic Form Local Computation Via Partial Boolean Difference Generating Reed-Muller Expressions by Logic Taylor Series Arithmetic Analogs of Boolean Differences and Logic Taylor Expansion Summary Problems Further Reading References NANODIMENSIONAL MULTIVALUED CIRCUITS Introduction to Multivalued Logic Spectral Technique Multivalued Decision Trees and Decision Diagrams Concept of Change in Multivalued Circuits Generation of Reed-Muller Expressions Linear Word-level Expressions of Multivalued Functions Linear Nonarithmetic Word-level Representation of Multivalued Functions Summary Problems Further Reading References PARALLEL COMPUTATION IN NANOSPACE Data Structures and Massive Parallel Computing Arrays Linear Systolic Arrays for Computing Logic Functions Computing Reed-Muller Expressions Computing Boolean Differences Computing Arithmetic Expressions Computing Walsh Expressions Tree-Based Network for Manipulating a Switching Function Hypercube Arrays Summary Problems Further Reading References FAULT-TOLERANT COMPUTATION Definitions Probabilistic Behavior of Nanodevices Neural Networks Stochastic Computing Von Neumanns Model on Reliable Computation with Unreliable Components Faulty Hypercube-Like Computing Structures Summary Further Reading References INFORMATION MEASURES IN NANODIMENSIONS Information-Theoretical Measures at Various Levels of Design in Nanodimensions Information-Theoretical Measures in Logic Design Information Measures of Elementary Switching Functions Information-Theoretical Measures in Decision Trees Information Measures in the N-Hypercube Information-Theoretical Measures in Multivalued Functions Summary Problems Further Reading References INDEX

Technique of computing logic derivatives for MVL-functions

A technique to compute logic derivatives of MVL-functions is considered based on four algorithms, two of them are new. At first these are symbolic and matrix algorithms to find logic derivatives with respect to variables, and, secondly, partial direct and inverse derivatives. The algorithms are compared by using an example of testing a MVL switching circuit. The matrix approach allows to extract the appropriatenesses of computing process and to come to some simple operators of logic processing truth vectors of MVL functions.

Facial biometrics for situational awareness systems

This study contributes to developing the concept of decision-making support in biometric-based situational awareness systems. Such systems assist users in gathering and analysing biometric data, and support the decision-making on the human behavioural pattern and/or authentication. As an example, the authors consider a facial biometric assistant that functions based on multi-spectral biometrics in visible and infrared bands; it involves facial expression recognition, face recognition in both spectra, as well as estimation of physiological parameters. The authors also investigate usage of facial biometrics for the semantic representation for advanced decision-making.

Experience of Design and Prototyping of a Multi-Biometric Early Warning Physical Access Control Security System (PASS) and a Training System (T-PASS)

This paper presents a concept of biometric-based early-warning and intelligent support for physical access security system (PASS). The early warning principle exploits the real-time analysis of the biometrics of the individual being scanned. Binding all sources of information into an objective supported by intelligence tools not only provides for reliable identification of an individual, but also supplies data for situational awareness and risk management support. An intelligent approach serves for interpretation of biometric data in semantic form, as well as dialogue support between the officer and the customer. The training-extended PASS (T-PASS) is built on the PASS, and aims at assisting the security personnel in developing decision making skills. The PASS and T-PASS are directed at a wide spectrum of applications such as immigration service and border control airports, seaports, border-crossing, security of important public events, hospitals and banking

Biometric-Enabled Authentication Machines: A Survey of Open-Set Real-World Applications

This paper revisits the concept of an authentication machine (A-machine) that aims at identifying/verifying humans. Although A-machines in the closed-set application scenario are well understood and commonly used for access control utilizing human biometrics (face, iris, and fingerprints), open-set applications of A-machines have yet to be equally characterized. This paper presents an analysis and taxonomy of A-machines, trends, and challenges of open-set real-world applications. This paper makes the following contributions to the area of open-set A-machines: 1) a survey of applications; 2) new novel life cycle metrics for theoretical, predicted, and operational performance evaluation; 3) a new concept of evidence accumulation for risk assessment; 4) new criteria for the comparison of A-machines based on the notion of a supporting assistant; and 5) a new approach to border personnel training based on the A-machine training mode. It offers a technique for modeling A-machines using belief (Bayesian) networks and provides an example of this technique for biometric-based e-profiling.

Information theory method for flexible network synthesis

We introduce a novel approach to extend flexibility of combinational multi-level networks synthesis based on information-theoretical measure (ITM). This problem is related to optimization for combinational multi-level networks, artificial evolution and machine learning in circuitry design. Using ITMs, we verify not only that an evolved network achieves the target functionality, but also that this network can be corrected in a simple regular way to achieve it. We demonstrate experimental results by evolutionary strategy on gate-level network design: effectiveness in evolved valid networks increases dozens of times.

Information theoretic approach to minimization of polynomial expressions over GF(4)

This paper addresses a new information theoretic approach to minimization of polynomial expressions for Multiple Valued Logic (MVL) functions. Its focus is to determine the so-called pseudo Reed-Muller and pseudo Kronecker expressions of MVL functions. A key point of our approach is the use of information theoretic measures for efficient design of Decision Trees (DTs) to represent MVL functions. We utilize free pseudo Reed-Muller GF(4) (PSDRMGF) DTs and free pseudo Kronecker GF(4) (PSDKGF) DTs. Furthermore, we show that the suggested approach allows to manage the process of minimization in a simple way, for the most of known forms of logic function representation. Our program, Info-MV, produces, in most cases, the extremely better results, in contrast to some known heuristic minimization strategies.

Comments on "Sympathy: fast exact minimization of fixed polarity Reed-Muller expansion for symmetric functions"

The above paper finds an optimal fixed-polarity Reed-Muller expansion of an n-variable totally symmetric function using an OFDD-based algorithm that requires O(n/sup 7/) time and O(n/sup 6/) storage space. However, an algorithm based on Supruns transient triangles requires only O(n/sup 3/) time and O(n/sup 2/) storage space. An implementation of this algorithm yields computation times lower by several orders of magnitude.

Experiments on FPRM expressions for partially symmetric logic functions

This paper focuses on the fired polarity Reed-Muller (FPRM) expression of multiple-valued logic (MVL) symmetric functions. In the FPRM expression, each variable occurs in exactly one complemented form. We show properties of the FPRM of partially symmetric functions and report experimental results for certain benchmark functions.