Vladimir Szekely

An efficient thermal simulation tool for ICs, microsystem elements and MCMs: the μS-THERMANAL

Integrated microsystems raise new problems in thermal simulation. The frequently used structures such as cantilevers and membranes have different heat transfer properties than the simple silicon cubes of conventional integrated circuits (ICs). To take advantage of this, numerous functions are realized on these structures based on the thermal principle. Quick and correct thermal simulation of these structures is needed during the design process. The paper presents the μS-THERMANAL thermal simulation tool which is capable of simulating, beyond the IC chips and three-dimensional multi-chip module packaging structures, the cantilever, the bridge and the membrane structures as well, both in steady-state and in the frequency-domain case. The algorithms of the program, based on the Fourier method, are detailed in the paper and numerous examples illustrate the capabilities of the tool.

Electro-thermal simulation: a realization by simultaneous iteration

After a comparison of major strategies of electro-thermal simulation (the relaxation method and the method of simultaneous iteration) a detailed description of the fundamentals and realization issues of the simultaneous iteration method is given. The paper introduces the SISSSI electro-thermal simulation package which is a recent realization of the latter method, fully integrated into the Cadence Opus design framework. The use of the package as an analogue circuit layout design verification tool is demonstrated through a detailed case study.

Thermal testing methods to increase system reliability

The scaling down of ICs and the increased packaging densities have resulted in increased concern about thermal issues during the design of ICs and their packages. In this paper newly developed design and testing methods are presented. The SISSSI electro-thermal simulator predicts the layout dependent electro-thermal behaviour of circuits. The presented CMOS temperature sensors and the idea of DFTT designs assure on-line temperature monitoring of circuits and packages. Also presented is a thermal transient testing method enables accurate thermal characterization of packages both for design and verification purposes. The capabilities of the new tools are demonstrated with application examples.

Design issues of a multi-functional intelligent thermal test die

Thermal characterization of IC packages and packaging technologies is becoming a key task in thermal engineering. To support this by measurements, we developed a family of thermal test chips that allows a wide range of possible applications. Our chips are based on the same basic cell that is mainly covered by dissipating resistors and also contains a frequency output temperature sensor. These basic cells are organized into arrays of different size. The arrays are designed so that larger arrays can also be built for tiling up larger package cavities. The first member of the family, TMC81, has been manufactured and measurements show that the goals aimed for at the design stage have been achieved.

Application results of a new thermal benchmark chip

A 1.2 /spl mu/m CMOS thermal benchmark chip has been designed, fabricated and tested. The chip is aimed at supporting various steady-state and transient measurements, e.g. surface temperature gradients, heating and cooling curves, in-chip thermal couplings, etc. It facilitates the calibration of various types of chip temperature mapping equipment. After the presentation of the chip design, experimental results are shown and evaluated in order to demonstrate the wide applicability of this measurement support tool.

New way for thermal transient testing [IC packaging]

This paper introduces a new concept of thermal transient measurement of IC packages without a tester. The thermal transient test kit described here consists of a test chip, dedicated software running on a PC and a special cable connecting the PC to the IC package which encapsulates the test chip. The functionality of the thermal transient test equipment is realized by the test chip itself and the measurement software. The software performs both the control of the measurement and the results evaluation. The final output of the evaluation software is a compact model network and the structure function, describing the properties of the heat conduction path realised by the IC package under test. The use of the test kit and the capabilities of its evaluation software are demonstrated by a few examples.

Co-simulation of dynamic compact models of packages with the detailed models of printed circuit boards

Presents an algorithm for the co-simulation of packages given with the RC compact models and the printed circuit boards. This enables on one hand the correct detailed consideration of the heat transfer in the board, on the other hand the calculation of the exact junction temperatures within the packages. Considering individual heat transfer coefficients for each package, or even to each side of the packages is possible. The main advantage is that the methodology keeps the fastness and user friendliness of the board level solvers, while giving information also about the details of the temperatures within or at the surfaces of the packages.

Algorithmic extension of thermal field solvers: time constant analysis

The time-constant spectrum representation is a useful description of the dynamic thermal behavior of packages, assemblies and microsystems. The paper presents the idea of the time constant spectrum representation of microelectronic structures, and provides an algorithm that can be used for time constant spectrum calculation in thermal simulator programs. Simulation examples demonstrate the applicability of the method.

New level of accuracy in TIM measurements

The thermal management of semiconductor devices and systems has become a widely discussed topic over the past decades due to the ever increasing integration and the resulting power densities inside the packages. The increasing junction temperature is a great threat for the operation and the long-term reliability of the packaged device. One of the most important barriers in the heat conduction path is the thermal interface material. Their thermal performance significantly influences the overall thermal resistance of a system from the junction to the ambient. In this paper two approaches are described for the accurate thermal conductivity measurement of these materials; both techniques were developed in the framework of the European Nanopack project. One of them is a highly accurate, scientific method which benefits from the improvements of the semiconductor industry: the TIM is measured between two bare sensor chip surfaces. The other method is based on thermal transient testing and allows the measurement of a given grease or paste in its real environment. Both of them are capable of the measurement of highly conductive, nanoparticle based TIM materials. In this paper these two methods are explained in more details and measured results are compared with each-other. The effect of the measurement arrangement on the measured thermal resistance values is also discussed.

Trends in Thermal Management of Microcircuits

With silicon microtechnology we intend to realize electrical networks: these are the integrated circuits. This goal however can never be obtained solely — a thermal network is also generated necessarily. The electrical parts dissipate heat, this will be the source of the thermal network. As a result the temperature of the chip will increase, changing the electrical parameters. In some cases this can even result in burning out the elements. With the decreasing chip feature sizes and package dimensions, with the increasing integration density the heat production per unit volume increases — continuously enlarging the severity of these problems.