Vlastimil Babka

Investigating Cache Parameters of x86 Family Processors

The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance engineering efforts. Unfortunately, the detailed parameters of the memory architecture are often not easily available, which makes it difficult to design experiments and evaluate results when the memory architecture is involved. To remedy this lack of information, we present experiments that investigate detailed parameters of the memory architecture, focusing on such information that is typically not available elsewhere.

On the accuracy of cache sharing models

Memory caches significantly improve the performance of workloads that have temporal and spatial locality by providing faster access to data. Current processor designs have multiple cores sharing a cache. To accurately model a workload performance and to improve system throughput by intelligently scheduling workloads on cores, we need to understand how sharing caches between workloads affects their data accesses. Past research has developed analytical models that estimate the cache behavior for combined workloads given the stack distance profiles describing these workloads. We extend this research by presenting an analytical model with contributions to accuracy and composability - our model makes fewer simplifying assumptions than earlier models, and its output is in the same format as its input, which is an important property for hierarchical composition during software performance modeling. To compare the accuracy of our analytical model with earlier models, we attempted to reproduce the reported accuracy of those models. This proved to be difficult. We provide additional insight into the major factors that influence analytical model accuracy.

When Misses Differ: Investigating Impact of Cache Misses on Observed Performance

Although modeling of memory caches for the purpose of cache design and process scheduling has advanced considerably, the effects of cache sharing are still not captured by common approaches to modeling of software performance. One of the obstacles is lack of information about the relationship between cache misses, which the cache models usually describe, and the timing penalties, which the performance models require. Following earlier work that has shown how cache misses do not quite account for timing penalties, we report on extensive experiments that investigate the connection between cache sharing and observed performance in more depth on a real computer architecture.

Can linear approximation improve performance prediction

Software performance evaluation relies on the ability of simple models to predict the performance of complex systems. Often, however, the models are not capturing potentially relevant effects in system behavior, such as sharing of memory caches or sharing of cores by hardware threads. The goal of this paper is to investigate whether and to what degree a simple linear adjustment of service demands in software performance models captures these effects and thus improves accuracy. Outlined experiments explore the limits of the approach on two hardware platforms that include shared caches and hardware threads, with results indicating that the approach can improve throughput prediction accuracy significantly, but can also lead to loss of accuracy when the performance models are otherwise defective.

Timing penalties associated with cache sharing

Although important from software performance perspective, the behavior of memory caches is not captured by the common approaches to modeling of software performance, where the software performance models tend to treat operation durations as constants despite the fact that the operations compete for memory caches. Incorporating memory cache models into software performance models is hindered by the fact that existing cache models do not provide information about timings and penalties, but only about hits and misses. The paper outlines the relationship of cache events and cache timings on a real computer architecture, indicating that the existing practice of modeling cache miss penalties as constants is not sufficient to model software performance faithfully.

Validating model-driven performance predictions on random software systems

Software performance prediction methods are typically validated by taking an appropriate software system, performing both performance predictions and performance measurements for that system, and comparing the results. The validation includes manual actions, which makes it feasible only for a small number of systems. To significantly increase the number of systems on which software performance prediction methods can be validated, and thus improve the validation, we propose an approach where the systems are generated together with their models and the validation runs without manual intervention. The approach is described in detail and initial results demonstrating both its benefits and its issues are presented.

Resource sharing in performance models

In software systems, individual components interact not only through explicit function invocations, but also through implicit resource sharing. The use of shared resources significantly influences the duration of the invoked functions. For resources that are heavily shared, capturing this influence can lead to performance models that have a large number of elements and a large number of dependencies. We introduce an approach that can model resource sharing separately from function invocations, keeping the performance model reasonably simple while still describing many of the effects of resource sharing on the duration of function invocations. The approach has been tested on the CoCoME component application modeling example.

Computer memory: why we should care what is under the hood

The memory subsystems of contemporary computer architectures are increasingly complex --- in fact, so much so that it becomes difficult to estimate the performance impact of many coding constructs, and some long known coding patterns are even discovered to be principally wrong. In contrast, many researchers still reason about algorithmic complexity in simple terms, where memory operations are sequential and of equal cost. The goal of this talk is to give an overview of some memory subsystem features that violate this assumption significantly, with the ambition to motivate development of algorithms tailored to contemporary computer architectures.

Teaching operating systems: student assignments and the software engineering perspective

This paper is an experience report outlining a transformation of an operating systems course in a systems oriented master study program. We present the initial and current stages of the transformation and summarize the lessons learned throughout the process. To illustrate the effects of the transformation, we provide feedback gathered from the students who have completed the course during the transformation. We put emphasis on general software engineering experience, which may prove useful in balancing the many issues related to most courses with programming assignments.