Volkan H. Ozguz

Rapid thermal annealing of arsenic and boron‐implanted silicon

Annealing of ion implantation damage and concomitant electrical activation of dopants, depth profiles, and lattice location of dopants have been studied in arsenic and boron‐implanted specimens after rapid thermal annealing. A ‘‘complete’’ annealing of displacement damage with full electrical activation of dopants and profile broadening less than 100 A can be attained for shallow implants whereas some extended defects are retained for deep implants. Mechanisms of rapid thermal annealing and its implications in solid state device fabrication are discussed.

Digital free-space optical interconnections: a comparison of transmitter technologies

We investigate the performance of free-space optical interconnection systems at the technology level. Specifically, three optical transmitter technologies, lead-lanthanum-zirconate-titanate and multiple-quantum-well modulators and vertical-cavity surface-emitting lasers, are evaluated. System performance is measured in terms of the achievable areal data throughput and the energy required per transmitted bit. It is shown that lead-lanthanum-zirconate-titanate modulator and vertical-cavity surface-emitting laser technologies are well suited for applications in which a large fan-out per transmitter is required but the total number of transmitters is relatively small. Multiple-quantum-well modulators, however, are good candidates for applications in which many transmitters with a limited fan-out are needed.

Three-dimensional optoelectronic stacked processor by use of free-space optical interconnection and three-dimensional VLSI chip stacks

We present a demonstration system under the three-dimensional (3D) optoelectronic stacked processor consortium. The processor combines the advantages of optics in global, high-density, high-speed parallel interconnections with the density and computational power of 3D chip stacks. In particular, a compact and scalable optoelectronic switching system with a high bandwidth is designed. The system consists of three silicon chip stacks, each integrated with a single vertical-cavity-surface-emitting-laser-metal-semiconductor-metal detector array and an optical interconnection module. Any input signal at one end stack can be switched through the central crossbar stack to any output channel on the opposite end stack. The crossbar bandwidth is designed to be 256 Gb/s. For the free-space optical interconnection, a novel folded hybrid micro-macro optical system with a concave reflection mirror has been designed. The optics module can provide a high resolution, a large field of view, a high link efficiency, and low optical cross talk. It is also symmetric and modular. Off-the-shelf macro-optical components are used. The concave reflection mirror can significantly improve the image quality and tolerate a large misalignment of the optical components, and it can also compensate for the lateral shift of the chip stacks. Scaling of the macrolens can be used to adjust the interconnection length between the chip stacks or make the system more compact. The components are easy to align, and only passive alignment is required. Optics and electronics are separated until the final assembly step, and the optomechanic module can be removed and replaced. By use of 3D chip stacks, commercially available optical components, and simple passive packaging techniques, it is possible to achieve a high-performance optoelectronic switching system.

Alignment issues in packaging for free-space optical interconnects

The addition of optics to electronics in optoelectronic packaging for free-space optical interconnects alters the nature of electrical packaging design methodologies as well as the complexity of implementation. One such complexity arises from the stringent alignment requirement among the microlaser, computer-generated holographic element, and detector. The alignment achieved in the system is a function of assembly tolerance and working environment conditions such as operating temperature. The impact of these constraints on the alignability of the assembly of free-space optical interconnects is quantitatively analyzed.

Deposition and characterization of thin ferroelectric lead lanthanum zirconate titanate (PLZT) films on sapphire for spatial light modulators applications

Ferroelectric lead lanthanum zirconate titanate (PLZT) films are deposited on R-plane sapphire using RF triode magnetron sputtering. Perovskite PLZT films with the desired composition (9/65/35) are obtained using compensated deposition techniques around 500 degrees C and postdeposition annealing at 650 degrees C. The deposited films exhibit good optical and electrooptical properties. The room temperature dielectric constant of the films was 1800 at 10 kHz. The refractive index of the films was in the range of 2.2-2.5. The films showed a quadratic electrooptic effect with R=0.6 *10/sup -16/ m/sup 2//V/sup 2/. The development of PLZT on silicon-on-sapphire smart spatial light modulators using these films is also explored.<<ETX>>

Tolerancing of board-level-free-space optical interconnects

For optical interconnects to become a mature technology they must be amenable to electronic packaging technology. Two main obstacles to including free-space optical interconnects are alignment and heat-dissipation issues. Here we study the issues of alignment tolerancing that are due to assembly and manufacturing variations (passive-element tolerancing) over long board-level distances (>10 cm) for free-space optical interconnects. We also combine these variations with active optoelectronic device variations (active-element tolerancing). We demonstrate a computer-aided analysis procedure that permits one to determine both active- and passive-element tolerances needed to achieve some system-level specification, such as yield or cost. The procedure that we employ relies on developing a detailed design of the system to be studied in a standard optical design program, such as code v. Using information from this model, we can determine the integrated power falling on the detector, which we term optical throughput, by performing Gaussian propagation or general Fresnel propagation (if significant vignetting occurs). This optical throughput can be used to determine system-level performance criteria, such as bit-error rate. With this computer-aided analysis technique, a sensitivity analysis of all the variations under study is made on a system with realistic board-level interconnect distances to find each perturbations relative effects (with other perturbations set to 0) on the power falling on the detector. This information is used to set initial tolerances for subsequent tolerancing analysis and design runs. A tolerancing analysis by Monte Carlo techniques is applied to determine if the yield or cost (yield is denned as the percentage of systems that have acceptable system performance) is acceptable. With a technique called parametric sampling, a subsequent tolerancing design run can be applied to optimize this yield or cost with little increase in computation. We study a design example and show that most of the tolerances can be achieved with current technology.

Design issues and development of monolithic silicon/lead lanthanum zirconate titanate integration technologies for smart spatial light modulators

System, device, and material issues for the design and realization of smart spatial light modulators are discussed. Silicon and lead lanthanum zirconate titanate (PLZT) are two promising materials that meet the system requirements. Two different technologies for the integration of Si and PLZT are described. Results show that large-scale smart spatial light modulators can be realized with Si/PLZT technologies.

Electrical properties of implanted and rapid thermal annealed shallow p+‐n junctions

The electrical properties of shallow junctions fabricated using a 50‐keV BF2 ion implantation into 〈100〉 n‐Si followed by rapid thermal annealing (RTA) have been investigated. The junction depth was 0.25 μm. Sheet resistance measurements have shown that annealing at 950 °C for only 10 s results in approximately 90% electrical activation. In addition this annealing cycle gives the optimum leakage current. The leakage current density obtained was 1 fA/μm2 (at 10‐V reverse bias voltage, for 2–4‐Ω cm n‐type substrate). The results indicate that RTA can be used to obtain reproducible shallow junctions without significantly changing the implanted profile.

High power chip stacks with interleaved heat spreading layers

3-D chip packaging and optoelectronic array interconnect technologies can be combined to realize ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. Thermal management is becoming a key issue if the active volume is minimized. The use of CVD diamond layers as a thermal management tool for the implementation of 3D stacks has been demonstrated to allow up to 80 W power dissipation in densely packed stacks of less than 1 cm/sup 3/.

Design considerations and algorithms for partitioning optoelectronic multichip modules

There is considerable interest in the development of optical interconnects for multichip modules (MCMs) to improve their performance. For effective utilization of the optical and electronic technologies, a methodology for partitioning the system is required. The key question to be answered is which technology should be used for each interconnect in a given netlist: optical or electronic. We introduce the computer-aided design approach for partitioning optoelectronic systems into optoelectronic MCMs. We first discuss the design trade-off issues in an optoelectronic system design, including speed, power dissipation, area, and diffraction limits for free-space optics. We then define a formulation for optoelectronic MCM partitioning and describe new algorithms for optimizing this partitioning based on the minimization of the power dissipation. The models for the algorithms are discussed in detail, and an example of a multistage interconnect network is given. Different results, with the number and size of chips being variable, are presented in which improvement for the system packaging has been observed when the partitioning algorithms are applied.