Vyasa Sai

Low power 8051-MISA-based remote execution unit architecture for IoT and RFID applications

Using the existing microcontrollers in radio frequency identification (RFID)-based passive nodes requires too much power. There is a need to explore specific instruction sets of such microcontrollers based on target applications for low power. In this context, this paper describes a low-power wireless distributed single instruction multiple data (SIMD) architecture concept. This concept involves having the data and program instructions stored on a powered interrogator providing wireless supervisory control for the passive node that has a basic processing core called the remote execution unit (REU). This paper also proposes a novel REU architecture using a minimal instruction set architecture (MISA) based on 8051 µC with the goal of reducing power consumption of a wireless passive node. Post-layout simulation results indicate significant reduction in power consumption and the area occupied by REU when compared to an existing 8051 core design. This low-power programmable REU architecture targets internet of things (IoT) and passive RFID applications.

Serial Data Driven Cyclic Redundancy Check Generator for Low Power RFID Applications

Cyclic Redundancy Checks (CRCs) are commonly used for their effective error-detecting capabilities in various wireless transceivers, digital networks, data storage devices, embedded designs, RFID systems, etc. The conventional clock-driven and combinational logic based CRC hardware implementations are known to consume considerable power especially those used in wireless passive devices. This paper proposes a low-power implementation of a novel serial data driven CRC for passive RFID tags. This CRC design is not explicitly clocked, but driven by the incoming encoded data as opposed to clock recovery. The associated CRC computations are done in parallel to the data decoding procedure unlike the traditional shift register implementations. Simulation results of the data driven CRC-16 design show significant reduction in power consumption and the area occupied as compared to the typical CRC-16 implementations used in RFID applications.

Low-power smart passive REU for industrial IoT applications

Energy management at passive terminal nodes is a critical design goal in the industrial internet of things (IoT) network. This article introduces a programmable low power remote execution unit (REU) based on an 8051 instruction set architecture (ISA) for passive radio frequency identification (RFID) applications in industrial IoT. The REU acts as a passive device processor requiring the interrogator to transmit instructions to be executed over a wireless link. This paper investigates the proposed asynchronous REU implementation with respect to the power consumption, area and speed and also provides a performance comparison to an existing clocked REU implementation. Based on the post-layout simulation results, the proposed asynchronous REU has lower power consumption when compared to the clocked REU operating at higher frequencies. Such a low power REU in the context of passive processing has a significant impact on IoT, a ubiquitous industrial application of RFID technology.

Ultra High-Speed and Low-Power Flexible Architecture using State Transition Matrix Model for EPC Gen-2 Communication Protocol Processor

Abstract In modern electronics, communication between systems is progressing towards wireless technology [1]. The rapid adaptation of the Wi-Fi technology across the world is a good example of the trends to come [2]. The IEEE 802.11 protocol [3], with its different layers of communication (information transfer), is obviously not ideal for applications that are time and energy sensitive. The EPCglobal Class-1 Generation-2 Protocol [4] (adapted by the International Organization for standards as the ISO 18000-6 [5]) is an impressive alternative that is slowly gaining global recognition as not just an RFID protocol, as it was primarily intended for, but as a front-end (communication link) for several identification and sensor applications [6]. This paper reports the design of a low-power processor specific for the Gen-2 instruction set with high emphasis on speed optimization at low power consumption. A novel approach in processor design as an asynchronous state machine is introduced, making the architecture extremely flexible and adaptable to changes in the protocol. Given that the full Gen-2 state transition matrix is available with direct linkage to the published standard, changes in the protocol can be directly effected through this matrix. Thus, the generation or the original and updated VLSI chips with the design flow disclosed is simply a matter of using the original or updated matrix. The design of the processor from a hardware description language (VHDL) level makes the final implementation possible either as an ASIC or on a suitable FPGA. The ASIC design flow is considered in this paper reporting the three fundamental characteristics—speed, power and area, of the post layout design. Industry standard Mentor Graphics ModelSim SE, Synopsys Design Compiler and Cadence Encounter are used in this research.