W. C. Holton

DEUTSCH-JOZSA ALGORITHM AS A TEST OF QUANTUM COMPUTATION

A redundancy in the existing Deutsch-Jozsa quantum algorithm is removed and a refined algorithm, which reduces the size of the register and simplifies the function evaluation, is proposed. The refined version allows a simpler analysis of the use of entanglement between the qubits in the algorithm and provides criteria for deciding when the Deutsch-Jozsa algorithm constitutes a meaningful test of quantum computation.

Ensemble Monte Carlo study of channel quantization in a 25-nm n-MOSFET

We develop a self-consistent, ensemble Monte Carlo device simulator that is capable of modeling channel carrier quantization and polysilicon gate depletion in nanometer-scale n-MOSFETs. A key feature is a unique bandstructure expression for quantized electrons. Carrier quantization and polysilicon depletion are examined against experimental capacitance-voltage (C-V) data. Calculated drain current values are also compared with measured current-voltage data for an n-MOSFET with an effective channel length (L/sub eff/) of 90 nm. Finally, the full capabilities of the Monte Carlo simulator are used to investigate the effects of carrier confinement in a L/sub eff/=25 nm n-MOSFET. In particular, the mechanisms affecting the subband populations of quantized electrons in the highly nonuniform channel region are investigated. Simulation results indicate that the occupation levels in the subbands are a strong function of the internal electric field configurations and two-dimensional (2-D) carrier scattering.

An optically driven quantum dot quantum computer

We propose a design for a quantum computer that builds on n-type SET structures reported by Tarucha et al. (1996). Our design consists of an array of free standing pillars with source and drain electrodes at the top and bottom of the pillar and a stacked series of asymmetric GaAs/AlGaAs quantum wells arrayed along the axis. By applying a negative bias to the cylindrical gate electrode, carriers near the surface are depleted. The parabolic electrostatic potential provides confinement in the radial direction while bandgap discontinuities in the quantum wells provide confinement along the pillar axis. In operating as a quantum computer the source and drain are grounded and the number of electrons in each dot are set to one by adjusting the gate voltage. Qubits are encoded in the ground state and first excited state of the quantum dot electrons. The pillar array constitutes an ensemble of quantum computers that operate simultaneously.

Scaling trends for device performance and reliability in channel-engineered n-MOSFETs

Channel-engineered MOSFETs with retrograde doping profiles are expected to provide increased carrier mobility and immunity to short channel effects. However, the physical mechanisms responsible for device performance of retrograde designs in the deep-submicron regime are not fully understood, and general device scaling trends are not well documented. Also, little effort has been devoted to the study of hot-electron-induced device degradation. In this paper, we employ a comprehensive simulation methodology to investigate scaling and device performance trends in channel-engineered n-MOSFETs. The method features an advanced ensemble Monte Carlo device simulator to extract hot-carrier reliability for super-steep-retrograde and more conventional silicon n-MOS designs with effective channel lengths scaled from 800 to 100 nm. With decreasing channel length, our simulations indicate that the retrograde design shows increasingly less total hot-electron injection into the oxide than the conventional design. However, near the 100-nm regime, the retrograde design provides less current drive, loses its advantage of higher carrier mobility, and exhibits much greater sensitivity to hot-electron-induced interface states when compared to the conventional device.

Temperature dependence of impact ionization coefficients in p-Si

An efficient full-band Monte Carlo program for high-energy carrier transport is employed to investigate hole impact ionization in p-Si for a range of electric fields up to 800 kV/cm and lattice temperatures between 77 and 450 K. An empirical expression is developed for the temperature dependence of ionization coefficients. The results are compared with those obtained from existing models. The empirical model agrees well with experiments and other numerically intensive models, providing a means to incorporate these effects into other device simulators and reliability models.

Analysis of hot-electron reliability and device performance in 80-nm double-gate SOI n-MOSFET's

In this paper, we employ a comprehensive Monte Carlo-based simulation method to model hot-electron injection, to predict induced device degradation, and to simulate and compare the performance of two double-gate fully depleted silicon-on-insulator n-MOSFETs (one with a lightly-doped channel and one with a heavily-doped channel) and a similar lightly-doped single-gate design. All three designs have an effective channel length of 80 nm and a silicon layer thickness of 25 mm. Monte Carlo simulations predict a spatial retardation between the locations of peak hot-electron injection into the front and back oxides. Since the observed shift is a significant portion of the channel length, the retardation effect greatly influences induced degradation in otherwise well-designed SOI devices. This effect may signal an important consideration for sub-100-nm design strategy. Simulations were also conducted to compare transistor performance against a key figure of merit. Evaluation of reliability and performance results indicate that the double-gate design with a lightly doped channel offers the best tradeoff in immunity to hot-electron-induced degradation and performance.