W. Hinrichs

A 1.3-GOPS parallel DSP for high-performance image-processing applications

In this paper, a programmable DSP for real time image processing is presented that combines the concepts of VLIW and SIMD with a high utilization of parallel resources on instruction level and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image processing requirements and follows two basic rules: Shared data have to be accessed regularly in shape of a matrix and are stored in the Matrix Memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The Matrix Memory allows parallel, conflict-free access from all datapaths in a single clock cycle. A first prototype of the DSP with four datapaths achieves 1.3 GOPS performance at 66 MHz, using a 0.5µm CMOS technology.

Realization of a programmable parallel DSP for high performance image processing applications

Architecture and design of the HiPAR-DSP, a SIMD controlled signal processor with parallel data paths, VLIW and novel memory design is presented. The processor architecture is derived from an analysis of the target algorithms and specified in VHDL on register transfer level. A team of more than 20 graduate students covered the whole design process, including the synthesizable VHDL description, synthesis, routing and backannotation as the development of a complete software development environment. The 175 mm/sup 2/, 0.5 /spl mu/m 3LM CMOS design with 1.2 million transistors operates at 80 MHz and achieves a sustained performance of more than 600 million arithmetic operations.

HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications

The presented HiPAR-DSP is a highly parallel DSP core for system on a chip video- and image processing applications. The architecture is based on an array of up to 16 parallel data paths steered by a single RISC controller in SIMD style. Each data path consists of three VLIW controlled arithmetical units: a 16 bit MAC and 32 bit ALU and shift & round units. A divided memory concept serves local caches for each data path as well as a special shared matrix memory which enables concurrent access from all data paths in every clock cycle. External connection can be provided via a modular DMA controller which enables an easy interfacing to other on chip modules. The HiPAR-DSP core has been manufactured in the most powerful version with 16 data paths in second Quarter 2001 and delivers with a maximum clock frequency of 100 MHz 4.8 GOPS peak and about 3 GOPS sustained performance. In addition to the core architecture the paper will also present the software development system for the HiPAR-DSP including C/C++ compiler, assembler, simulator and a PCI board with onboard video I/O interfaces.

Hipar-DSP-a scalable family of high performance DSP-cores

With the HiPAR-DSP family we present a scalable series of high performance fixed point DSPs. The HiPAR-DSP family features up to 16 SIMD controlled datapaths, where each datapath consists of a VLIW controlled set of arithmetic units (16 bit multiply and accumulate, 32 bit ALU and 32 bit shift and round). A shared on-chip memory with specially adapted parallel access is used for communication between the datapaths. The number of datapaths can easily be scaled to adapt the architecture to requirements in terms of processing power and silicon area. A flexible DMA control unit allows easy interfacing for systems on a chip. The maximum configuration of the presented DSP family can sustain a processing power of more than 3 GOPS for actual applications.

HiPAR-DSP 16: A parallel DSP for onboard real-time processing of synthetic aperture radar data

The authors present the HiPAR-DSP 16, a parallel and programmable architecture which is adapted to the demands of SAR image processing. To provide a high FFT performance, the HiPAR-DSP 16 features an array of 16 parallel processing units. Efficient data exchange between the processing units can be done by a shared memory with concurrent access. The HiPAR-DSP 16 is able to perform a range compression of 2100 lines (4k complex samples) per second. Therefore the HiPAR-DSP is one of the enabling technologies for onboard real-time processing of SAR images.

A multi DSP board for real time SAR processing using the HiPAR-DSP 16

At the University of Hannover a fully programmable DSP, the HiPAR-DSP 16, was developed. This HiPAR-DSP 16 contains 16 parallel datapaths and a 2-dimensional memory adapted to image processing algorithms. For real time SAR processing high computational power is required. Therefore a multi DSP board with 6 HiPAR-DSP 16 is developed. The high performance of up to 28 GOPS enables a SAR processing in real time. The calculation time for the wk-algorithm running on this board was estimated. For blocks of 4096 lines with 4096 8 bit complex samples real time processing is possible to a pulse repetition frequency (PRF) of 1200 Hz. Due to a low power consumption and the small size of 160/spl times/230 mm/sup 2/ of this board the use in on-board systems is predestinated.

HiPAR-DSP 16: a new DSP for onboard real-time SAR systems

In this paper we present the HiPAR-DSP 16, a parallel and programmable processor architecture which is adapted to the demands of SAR image processing. TO provide a high performance, the HiPAR-DSP 16 features an array of 16 parallel processing units. Each of these processing units can process up to 3 instructions per clock cycle. Efficient data exchange between the processing units can be done by a shared memory with concurrent access. The HiPAR-DSP 16 is able to perform a 4096 samples complex FFT in 154 microsecond(s) and a compete (omega) k SAR processing algorithm on 4k range line with a PRF of more than 200 Hz in real-time. This shows the high capability of the HiPAR-DSP 16 for onboard real-time SAR systems.

A compact and flexible multi-DSP system for real-time SAR applications

This paper presents a Multi-DSP system for real- time SAR-processing using the HiPAR-DSP 16. We developed this full programmable processor at the Laboratorium f ¨ ur Informationstechnologie. With 16 parallel data paths and a two- dimensional memory it is optimized for image processing algo- rithms like FFT-transforms. SAR image synthesis methods, like the investigated ωk-algorithm, use the computational intensive FFT-transform. To overcome the large processing power of future realtime SAR image synthesis applications, several DSPs have to work in parallel. The presentedcompact SAR system can be easily adapted to match the demands of different SAR algorithms by scaling the number of processing nodes. Equiped with 6 HiPAR-DSP 16 a 233x175x15 mm 3 boardprovid es a realtime capability of processing SAR applications with a PRF of 1200 Hz. A rangeline length of 4096 8 bit complex samples and 4096 rangelines is assumed. The small volume and its power consumption of less than 35 W enables it for on-boardusage in compact air- or spaceborne systems.

Implementation of real-time sar-systems with a high performance digital signal processor

Real-time Synthetic Aperture Radar (SAR) image synthesis is one of the major problems to solve in the future. To achieve a fully synthesized SAR image, the raw signal must be filtered with a 2-dimensional function representing the system transfer function. These filtering operations are usually processed by multiplication in frequency domain. Therefore, the Fast Fourier Transform (FFT) used for transformation to/from frequency domain is the predominant algorithm in terms of processing power for SAR image synthesis. The presented HiPAR- DSP is a programmable architecture, which is optimized for FFT-dominated applications like SAR image processing. To provide the high requested processing power for these task, the HiPAR-DSP has an array of 4 (HiPAR-DSP4) respectively 16 (HiPAR-DSP16) parallel processing units (datapaths) which is controlled by a single RISC Controller. For data exchange between the processing units there is a shared memory which allows the concurrent access from all processing units in a single clock cycle. So the HiPAR-DSP16 performs a complex FFT with 1024 Samples in 32microsecond(s) . For the implemented SAR- Processing task, the Range Compression with 4096 complex samples per line we achieve a real-time performance of nearly 1500 rangelines/s.

Multi-DSP board for compact real-time synthetic aperture radar systems

Real-time SAR processing requires high computational power. At the Laboratorium fur Informationstechnologie a parallel DSP called HiPAR-DSP 16 was developed, which is optimized for image processing algorithms. In this paper we present a compact multi-DSP board utilizing the HiPAR-DSP 16. The board can deliver a performance of up to 15 GOPS, has a volume of 160 X 230 X 20 mm, and consumes less than 20 W. The first version of the board is used for filtering of SAR data to show the capabilities of the system. An estimation showed that our board can process an wk algorithm with a rangeline length of 4096 samples and a PRF of 600 Hz in real-time.