W. Robertson

Energy conservation in clustered wireless sensor networks

In this paper, results from Walds equation and stochastic geometry are applied to the analysis of the energy expended in a homogeneous clustered Wireless Sensor Network (WSN). We determine the optimum number of clusterheads for minimising the energy expended by a single-hop clustered WSN in transmitting data to a sink using nonlinear and linear aggregation models, and include error control. Our model makes it possible to determine the optimum number of clusters given the node electronic energy expended, the type of aggregation employed, the propagation loss and the network geometry. The effect of these parameters on the optimum number of clusterheads is analysed. The analytical model is verified with simulations. We observe that, in some networks, clustering is not beneficial for minimising network energy.

A system for systolic modules for the MUSIC algorithm

The authors believe that special-purpose architectures for digital signal processing (DSP) real-time applications will use closely coupled processing elements as array processor modules to implement the various portions of the new algorithms, and several such modules will cooperate in a pipelined manner to implement complete algorithms. Such an architecture, based upon systolic modules, for the MUSIC algorithm is presented. The architecture is suitable for VLSI implementation. The throughput of the pipelined approach is O(N), whereas the sequential approach is O(N/sup 3/). >

A systolic architecture for the symmetric tridiagonal eigenvalue problem

The first step in the development of a chip set to support eigenvalue-eigenvector-based estimation algorithms is presented. It is based on the assumption that an averaging technique will produce a symmetric covariance matrix. Such a matrix can be reduced to a symmetric tridiagonal matrix, and hence the eigenvalues and eigenvectors can be found by successive iterations involving QR decomposition. The architecture is unique in that other architectures either solve only for the eigenvalues or use methods other than QR iteration. It has potential for use in a systolic computer for computer intensive digital signal processing based on modern spectral-analysis techniques.<<ETX>>

Improving temporal representation in TDNN structure for phoneme recognition

The authors deal with increasing the amount of temporal information that can be extracted by a time delay neural network in speech recognition problems. In addition to input time windows, frequency windows are considered for connection to the hidden units. Frequency windows are included to extract more information, such as the change in the energy contents over time of speech data at the grass-root level of the network. The proposed approach was verified by designing an unvoiced stop consonant classifier and evaluating it with continuous speech. Results are shown to demonstrate the viability of the approach.<<ETX>>

Subband filters using allpass structures

A novel design technique for multichannel power complementary filters using a minimum number of allpass sections is investigated and new results are reported in this context. In particular, specific power complementary design procedures are given for the three-band case using two allpass sections and for the four-band case using two as well as three allpass sections. In both cases a free variable allows the extra freedom to shape the filters to have the desired bandpass characteristics. This idea is illustrated in the three-band case by generating a lowpass, a bandpass, and a highpass power complementary filter combination using two allpass sections. These digital power complementary structures are attractive for VLSI design, since the actual number of filters to be implemented is smaller than that in a conventional design.<<ETX>>

A systolic MUSIC system for VLSI implementation

The authors review the MUSIC algorithm and introduce novel systolic modules required for its implementation. A complete system based on uniform time-sampled sum-of-sinusoid signals in Gaussian noise and the MUSIC algorithm is then discussed. Block processing, limited sampling interval, and serial-by-word communication between modules are assumed. Simulation results are compared with results obtained from conventional MUSIC algorithm computations. Comparison with results from an exact singular-value-decomposition program show no significant differences.<<ETX>>

The investigation of using limited precision on a TDNN for consonant recognition

This paper presents a fixed-point arithmetic implementation of consonant recognition in continuous speech with speaker independence. The most widely used neural network learning algorithm, backpropagation (BP), is utilized to train the neural network. The neural network employed here, time delay neural network (TDNN) consists of small sub networks designed to capture the coarticulatory effects of the speech data. The recognition of unvoiced stop consonants; P, T, K, is investigated by using the TIMIT speech data base with 18 speakers of 6 main dialects. Fixed-point simulation results deviate 1-2% from their floating-point counterparts. Overall success rate for the unvoiced stop consonants by using limited precision is between 80 and 90% for the test set.

RTL synthesis for systolic arrays

A register-transfer-level systolic synthesis strategy for multidimensional systolic arrays is described. Optimum utilization of silicon is attained by rescheduling operations on functional units across processing elements. The synthesis tool examines the tradeoff between sharing of functional units, additional buses, and the size of the controller.<<ETX>>

Mobility based scheduling for the register-transfer synthesis of systolic arrays

The authors present a novel scheduling and allocation algorithm for both one- and two-dimensional SUs (systolic units). This algorithm works across the PEs (processing elements) of an SU to reduce the number of FUs (functional units) required in an implementation. For the examples presented this technique results in fewer FUs and latches than if individual PEs were synthesized and then combined into an SU. In systolic arrays where the silicon area requirement of each PE is high, interlacing across PEs results in an implementation with a smaller design area. The interlacing (latch, controller, and multiplexer) area increases with interlacing up to a certain point. After this point, increased interlacing actually reduces the number of latches and multiplexers in the design, resulting in a drop in interlacing area. This is because in the proposed design strategy the latches are also interlaced in order to make the most efficient use of silicon.<<ETX>>

Systolic designs for speech processing

This paper presents a systolic system design for real-time computation of four speech parameters viz. energy, zero-crossing rate, coefficients of linear predictive coding (LPC) analysis and error of the LPC analysis of a speech segment, for applications in a real-time endpoint detection algorithm for isolated utterances and a real-time speaker-independent digit-recognition system. For a p-pole LPC analysis, the systolic system requires ((p/sup 2/+5p+6)/2) processors.<<ETX>>