Waleed K. Al-Assadi

Testing of Asynchronous NULL Conventional Logic (NCL) Circuits

Due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, conventional automatic test pattern generation (ATPG) algorithms would fail when applied to asynchronous circuits, leading to poor fault coverage. This paper focuses on design for test (DFT) techniques aimed at making asynchronous NCL designs testable using existing DFT CAD tools with reasonable gate overhead, by enhancing controllability of feedback nets and observability for fault sites that are flagged unobservable. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. The approach has been automated, which is essential for large systems; and are fully compatible with industry standard tools.

Analysis and Modeling of Crosstalk Noise in Domino CMOS Circuits

Domino CMOS logics offer designers with the advantage of most influential circuit design parameters viz., speed, higher integration density and lower power dissipation. This has made a common practice to use the domino CMOS in high performance integrated circuits. However, along with these positives comes inherently low crosstalk noise immunity. This reduced noise immunity of domino CMOS logics is continuously aggravating as recent trends in integrated circuit technology are constantly followed. Although several works investigate the problem of crosstalk noise at the inputs of domino circuits, crosstalk at the dynamic node of the domino circuits has been ignored. In this paper, we propose a model for crosstalk noise at the dynamic node of domino CMOS logic circuits. The model developed incorporates a newly derived switching threshold for the output static inverter in domino CMOS logics to more accurately predict the crosstalk noise immunity of the design. Application of this model can ensure immunity of domino circuits from crosstalk failures.

Development and Analysis of Defect Tolerant Bipartite Mapping Techniques for Programmable cross-points in Nanofabric Architecture

Chemically Assembled Electronic Nanotechnology (CAEN) using bottom-up approach for digital circuit design has imposed new dimensions for miniaturization of electronic devices. Crossbar structures or Nanofabrics using silicon nanowires and carbon nanotubes are the proposed building blocks for CAEN, sizing less than 20 nm, allowing at least 1010 gates/cm2. Along with the decrease in size, defect rates in the above architectures increase rapidly, demanding for an entirely different paradigm for increasing yields, viz. greater defect tolerance, because the defect rates can be as high as 13% or more. In this paper, we propose a non-probabilistic approach for defect tolerance and evaluate it in terms of its coverage for different sizes of fabric and different defect rates.

A BIST Technique for Crosstalk Noise Detection in FPGAs

As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is an important phenomenon that must be taken into account. Also, crosstalk noise has emerged as a serious problem in recent years, because more and more devices and wires have been packed on electronic chips. Despite being more immune to crosstalk noise than their ASIC (application specific integrated circuit) counterparts, the dense interconnected structures of FPGAs (field programmable gate arrays) invite more vulnerabilities to crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults caused by crosstalk noise. This paper proposes a new approach for detecting effects such as glitches and delays in transition due to crosstalk noise in FPGAs. This approach is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any extra overhead for testing.

NCL Implementation of Dual-Rail 2 S Complement 8×8 Booth2 Multiplier using Static and Semi-Static Primitives

In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e., threshold gates) to implement a dual-rail 8times8 2s complement multiplier using the Modified Booth2 algorithm for partial product generation and a Wallace tree for partial product summation. We establish the multipliers functionality utilizing VHDL-based simulations of the gate-level structural design. The design is then implemented at the transistor-level and layout-level using both static and semi-static threshold gates, for a 1.8V 0.18mum TSMC CMOS process; and these two implementations are compared in terms of area, power, and speed.

Secured Hardware Design - An Overview

Security is a prime concern in the design of a wide variety of embedded systems and security processors. So the customer security devices such as smart cards and security processors are prone to attack and there are on going research to protect these devices from attackers who intend to extract key information from these devices. Also an active attacker can induce errors during computation and exploit the faulty result to extract the key information embedded in the processor. Due to the design time issues weakness in the design is often revealed in the manufactured chips. Also because the post- manufacture security evaluation is time consuming and expensive, these security issues have to be considered at the design phase. This paper outlines some of the hardware attacks and provides a general idea of the process of these attacks.

A BIST Technique for Configurable Nanofabric Arrays

This work proposes a built-in self test (BIST) approach to test crossbars for a defined set of faults. The BIST can classify the different programmable elements in the crossbars as non-defective or defective with a certain fault type. The logic synthesis can then configure the crossbar by avoiding these defective elements.

Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Desig

Conventional Automatic Test Pattern Generation (ATPG) algorithms would fail when applied to asynchronous circuits due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, leading to poor fault coverage. This paper presents a Design for Test (DFT) approach aimed at making asynchronous NCL circuits testable using conventional ATPG tools when incorporated with synchronous-based designs. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.

Design of a flood prediction system

This paper explains the chip design of a flood prediction system based on piezoelectric pressure sensors. The sensors are placed at different water levels and can dependably predict the occurrence of a flood. The main criteria considered in the design of the system are low cost, low power consumption, ease of installation, autonomy, reliability, and most importantly, provision of early alerts. Predicting the flood before its actual occurrence can buy sufficient time for residents to evacuate nearby areas, preventing loss of life and property. The design has been prototyped on Alteras Cyclone DE2 FPGA board.

Modeling of Substrate Noise Effects in Dynamic CMOS Circuits

The decrease in the feature size has led to the integration of both digital and analog circuits on the same silicon die which has led to many crosstalk issues. The crosstalk due to the substrate interactions also plagiarizes complete digital systems. This paper lays emphasis on this fact and because of the vulnerability of dynamic CMOS circuits to noise; a brief study of the effects of substrate variations on the performance of the dynamic CMOS circuits is carried out in this paper. The effects of substrate noise at very high frequencies (above 10 GHz) are also depicted in this paper. In order to accurately estimate the effects of substrate noise a substrate model is proposed and verified for functionality in the last section of this paper.