Walter Demmer
Philips
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Publication
Featured researches published by Walter Demmer.
IEEE Journal of Solid-state Circuits | 1981
Horst L. Fiedler; B. Hoefflinger; Walter Demmer; Peter Draheim
Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.
Archive | 1985
Wilhelm Möring; Walter Demmer; Detlef Oldach
Archive | 1983
Walter Demmer; Rolf D. Gutsmann; Norbert A. Bergs; Ingolf Heinemann; Otto L. Warmuth
Archive | 1982
Jorg Wolber; Dieter Kunze; Friedrich Hahn; Walter Demmer
Archive | 1982
Jorg Wolber; Walter Demmer; Dieter Kunze; Friedrich Hahn
Archive | 1985
Walter Demmer; Rolf-Dieter Gutsmann; Jürgen Lenth
Archive | 1983
Walter Demmer; Thorwald Rabeler
Archive | 1988
Kurt-Joachim Johannes; Rolf-Dieter Gutsmann; Detlef Deutschmann; Otto L. Warmuth; Walter Demmer
Archive | 1987
Walter Demmer
Archive | 1987
Walter Demmer
