Walter Guggenbuhl

A high-swing, high-impedance MOS cascode circuit

A simple cascode with the gate voltage of the cascode transistor being controlled by a feedback amplifier called a regulated cascode is presented. In comparison to the standard cascode circuit, the minimum output voltage is lower by about 30 to 60% while the output conductance and the feedback capacitance are lower by about 100 times. An analytical large-signal, small-signal, and noise analysis is carried out. Some applications like current mirrors and voltage amplifiers are discussed. Experimental results confirming the theory are presented. >

A voltage-controllable linear MOS transconductor using bias offset technique

A linear large-signal MOS transconductor with the gain adjustable linearly by a voltage is described. A perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or single-ended input and differential output. Single-ended output is achievable by use of a current mirror. The nonlinearity caused by mobility reduction, channel-length modulation, mismatch, etc. is discussed. A test circuit with transconductance of 6.25 mu mho has been built with 3- mu m MOS components, and a linearity error of less than +or-1% was measured for an input voltage range from -4 to 4 V. >

An analog trimming circuit based on a floating-gate device

The application of floating-gate elements as adjustable components in analog CMOS circuits such as amplifiers is proposed. A simple trimming circuit based on this principle and delivering a differential current is described. Experimental results of a differential difference amplifier (DDA) containing two such circuits are given. After trimming, an offset voltage of 10 mu V and a nonlinearity of 0.1% are achieved. Other analog circuits based on floating-gate elements like adjustable voltage sources and transconductances have been realized. Because they can be electrically reprogrammed, a wide range of applications, for example in neural nets, are possible. >

All-night sleep EEG and artificial stochastic control signals have similar correlation dimensions ☆

EEG signals have been considered to be generated either by stochastic processes or by non-linear deterministic systems exhibiting chaotic behavior. To address this problem, the correlation dimension of the EEG was computed and compared to the correlation dimension of an artificial signal with identical power spectrum. By using a new type of personal super computer we were able for the first time to calculate the correlation dimension for the sleep episode of an entire night as well as for the corresponding artificial signal. The correlation dimension was high in episodes of rapid eye movement (REM) sleep, declined progressively within each non-REM sleep episode, and reached a low level at times when EEG slow waves (0.75-4.5 Hz) were dominant. The correlation dimension of the artificial signal and the EEG changed largely in parallel, although on average the values of the artificial signal were 7.3% higher. These results do not support the hypothesis that the sleep EEG is generated by a chaotic attractor.

Analog CMOS implementation of a multilayer perceptron with nonlinear synapses

A neurocomputer based on a high-density analog integrated circuit developed in a 3 mum CMOS technology has been built. The 1.6 mmx2.4 mm chip contains 18 neurons and 161 synapses in three layers, and provides 16 inputs and 4 outputs. The weights are stored on storage capacitors of the synapses. A formalization of the error back-propagation algorithm which allows the use of very small nonlinear synapses is shown. The influence of offset voltages in the synapses on the circuit performance is analyzed. Some experimental results are reported and discussed.

Fast neural net simulation with a DSP processor array

This paper describes the implementation of a fast neural net simulator on a novel parallel distributed-memory computer. A 60-processor system, named MUSIC (multiprocessor system with intelligent communication), is operational and runs the backpropagation algorithm at a speed of 330 million connection updates per second (continuous weight update) using 32-b floating-point precision. This is equal to 1.4 Gflops sustained performance. The complete system with 3.8 Gflops peak performance consumes less than 800 W of electrical power and fits into a 19-in rack. While reaching the speed of modern supercomputers, MUSIC still can be used as a personal desktop computer at a researchers own disposal. In neural net simulation, this gives a computing performance to a single user which was unthinkable before. The systems real-time interfaces make it especially useful for embedded applications.

Switched-current memory circuits for high-precision applications

We discuss circuit parameters that limit the precision of basic dynamic current-memory cells. In addition to analyzing current-copying errors caused by the finite output conductances of the current sources and by the clock-feedthrough (CFT) of the feedback switches, we analyze the noise performance of the basic memory cell. To reduce CFT and noise, we propose a novel circuit based on Miller capacitance-enhancement. Measurement results of memory cells integrated in a 1-/spl mu/m CMOS process confirm the theoretical findings; with our CFT and noise reduction technique based on Miller enhanced capacitance and dummy switches, we achieve a dynamic range of 11 b at clock frequencies greater than 100 kHz. >

A general relationship between amplifier parameters, and its application to PSRR improvement

A general relationship between the gains of multiterminal amplifiers is derived. This approach generates a constraint for the simultaneous improvement of the common-mode and the power-supply rejection ratio of the simple operational amplifier. This constraint can be relaxed by either adding a supplementary input terminal to the amplifier circuit or using a fully differential design. The method can be used to improve the power-supply rejection ratios in operational amplifiers. Several implementations of a two-stage operational amplifier illustrate this technique. >

Achieving supercomputer performane for neural net simulation with an array of digital signal processors

Music, a digital signal processor (DSP)-based system with a parallel distributed-memory architecture that provides enormous computing power yet retains the flexibility of a general-purpose computer, is discussed. It is shown that Music reaches a peak performance of 2.7 Gflops at a significantly lower cost, power consumption, and space requirement than conventional supercomputers. The Music system hardware, programming, and backpropagation implementation are described.<<ETX>>

Design and Construction of a Pulsed Ultrasonic Air Flowmeter

The construction and specific function of a new ultrasonic flowmeter are described. The mean velocity of the respiratory air flow is calculated by measuring the transit times of short ultrasonic pulse-trains simultaneously transmitted upstream and downstream at a 650 Hz rate. The flowmeter system consists of a control unit and a separate flowhead. The former includes the power supplies, a controlling microprocessor, most of the signal processing circuitry, and three analog outputs for flow, volume, and temperature, respectively. The flowhead contains the respiratory tube with a constant circular cross section (length 90 mm, diameter 20 mm, dead space 35 cm3), a fast temperature sensor, two electronic circuits for processing of flow and temperature data, and a sound transmission channel with two capacitive ultrasonic wide-band transducers. This respiratory air flowmeter is extremely fast (response time 1-2 ms) and accurate, with low noise (below 9ml/s), with a wide flow range (bidirectional from 0 to 9 l/s) and with a linear frequency response up to 70 Hz.