Walter Schwarzenbach

FDSOI: From substrate to devices and circuit applications

Nanotechnology starts at the substrate level. The SOI substrates enable performance improvement, area saving and power reduction for ICs through a convolution of substrate design and device architecture to maximize the benefits at the IC level. SOI substrates have made possible an efficient PDSOI MOSFET optimization increasing current drive while minimizing leakage and reducing parasitic elements. Further development of the SOI substrate technology has made possible to position ultra thin silicon SOI (UTSOI) as an industrial option for the manufacturing of FDSOI device architectures where the SOI film thickness uniformities is controlled below +5Å across the wafer and wafer to wafer. FDSOI enables the design for low power and high performance IC products. FDSOI circuit design does not have to take into consideration the history effect of PDSOI nor the high threshold voltage variation due to random dopant fluctuation given that the transistor channels are undoped. This makes the porting of designs from bulk to FDSOI much simpler. An overview of the advances in Smart Cut UTSOI and FDSOI devices and circuit applications will be given.

Strained silicon on insulator substrates for fully depleted application

Smart Cut™ technology is used to manufacture Strained-SOI (sSOI) substrates. These substrates are proposed to boost performance for both planar and FinFET Fully Depleted SOI devices. To comply with tight transistor variability requirements, strong emphasis has been put on layer thickness control and low stress variation. A 1.2 Å RMS roughness and less than 10% stress fluctuation are already demonstrated for sSOI wafers.

Defect inspection challenges and solutions for ultra-thin SOI

This paper will explain the challenges and solutions for ultra thin SOI inspection using a laser light scattering based system. The impact of reflectivity on haze, sizing and minimum threshold will be detailed. We will show how the required sensitivity for 28nm (and beyond node) SOI inspection was achieved using a commercially available unpatterned DUV inspection system. We will also study improvements in defect classification.

Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCutTM technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.

Evaluation of sSOI wafers for 22nm node and beyond

We assessed the performance of planar fully-depleted transistors built on sSOI wafers by comparing them to devices fabricated with the same process on SOI. A 23% increase in device performance was demonstrated, while maintaining at least as good device electrostatics and matching as SOI.

Ultra-thin SOI for 20nm node and beyond

Recent UTBB device data at sub-25nm gate length demonstrate good performance, small VT variation and excellent low power operation. In addition, very uniform Soitec Xtreme SOI™ product substrates are now available and compliant with device requirements. Thus the level of maturity of UTBB devices and substrates makes it possible for introduction at 20nm node. Multiple options at the substrate level to further boost the performance open up the path to improve performance for future nodes.

FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond

Multiples technology nodes in production are now based on FD-SOI thin film substrates. The development of these substrates has required several technical innovations (SmartCut process adaptation, new metrology introduction), which are discussed in this paper.

Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) [1] and ultra-low power Fully Depleted (FDSOI) [2], the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology [3]. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.

Investigation of hot carrier reliability of SOI and strained SOI transistors using back bias

In this paper, we investigate the potential of strained Silicon-On-Insulator for the future advanced CMOS nodes. Strained FDSOI devices not only exhibit a 30% higher performance in term of ION/IOFF but also show superior HC reliability at same drive current regardless of the back bias.

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

In this paper, we investigate the potential of strained Silicon-On-Insulator (sSOI) for the future advanced CMOS nodes. Strained FDSOI depicts a 30% higher performance in term of ION/IOFF thanks to higher mobility. Changes in band structure reduce the gate leakage and devices depict superior HC reliability at same drive current. The better interface quality with sSi layer leads to higher immunity to dangling bonds generation. Strain integration does not affect BTI and breakdown reliability.