Wan-Rone Liou

A Low-Voltage 5-GHz Quadrature Up-Conversion Mixer for Wireless Transmitter

In this paper, a low-voltage CMOS quadrature up-conversion mixer for 5-GHz wireless communication applications is designed. The simulation results demonstrate the mixer can reach a high conversion gain (CG), a low noise figure (NT), and a high linearity (IIP3). A miniature lumped- element microwave broadband rat-race hybrid and RLC shift network are used for the LO and the IF port design, respectively. The mixer exhibits a 3 dB improvement in noise and conversion gain, and the image rejection is -35 dBc. The mixer achieves noise figure of 12.8 dB, a conversion gain of 15 dB, an output third intercept point at 0 dBm, while dissipating 15 mW for operating voltage at 1 V. The mixer is designed with TSMC 0.18 um process.

Observation of negative differential resistance phenomenon in a two‐step barrier diode

In this work, the realization of AlxGa1−xAs/GaAs two‐step barrier diode is presented. Experimental observation on the current–voltage characteristics of the two‐step barrier diode is reported. At both room temperature and 77 K, it shows a strong negative differential resistance under forward bias while no similar phenomenon was observed under reverse bias. Such an asymmetric current–voltage characteristic would open the possibility of negative differential resistance in an ac field in the absence of a dc bias. Theoretical simulation and experimental current–voltage characteristics are compared and discussed.

The Study of Temperature Dependence of Second Harmonic Generation in Lead Lanthanum Titanate Thin Film by Corona Poling

Ferroelectric materials possess certain properties such as spontaneous polarization, domain structure, the hysteres is effect, and optical nonlinearity which attract much interest for research. Lead zirconate titanate (PZT) is one of the most researched materials for piezoelectric and electro optical applications. Recently, lanthanum modified lead titanate (PLT) has become popular because it possesses interesting properties such as a lower Curie temperature, a lower coercive field, and smaller remanent polarizations than PZT and has great potential for nonlinear optical and electro optical applications. PLT thin films were sputter deposited on fused silica substrate. We studied the second-order nonlinear optical properties in these thin films. The second harmonic generation intensities as a function of temperature were obtained. The optimum temperatures for obtaining the largest nonlinear optical coefficient have been found and the results are presented.

Second harmonic generation in barium titanate thin films on silica glass by corona poling

Among potential inorganic thin films, perovskite-structured barium titanate (BaTiO3) is particularly attractive due to its large ferroelectric response and large optical nonlinear coefficients. SiO2 material is also important in semiconductor processing. Therefore, we study the nonlinear optical (NLO) thin film deposited on a SiO2 substrate. We report our investigation of a BaTiO3 thin film on a silica glass (SiO2) substrate grown by rf magnetron sputtering. We measured the second-harmonic generation (SHG) and calculated the second-order nonlinear optical coefficients from the BaTiO3/glass by using the Maker fringes technique. From our experimental results, we found that by applying corona poling, the nonlinear optical coefficients in BaTiO3/glass can be increased. The SHG of the nonlinear thin film by poling is dependent on temperature.

A Low-Voltage Complementary-Metal–Oxide–Silicon 4.4-GHz Voltage Control Oscillator Design

A fully integrated 1 V, 4.4 GHz Inductor–Capacitor (LC) voltage control oscillator is designed for low-voltage high-frequency circuits and used in 5 GHz wireless LAN front-end system applications. An LC tank load is used in the oscillator design to decrease the power consumption. The measurement results show a tuning range from 3.903 GHz to 4.42 GHz for Vtf varying from 0 V to 1 V. The phase noise is -95 dB/Hz at 100 KHz. The bias voltage inside the chip has an additional capacitor to provide steady power and decrease the power noise injected into the output resonant signal. This oscillator is implemented using the TSMC 0.35 µm one-poly-four-metal 3.3 V logic process. The total chip area is 1.235×0.902 mm2.

Simulation and analysis of a high-frequency resonant tunneling diode oscillator

Abstract The large-signal response of resonant tunneling diodes at microwave and millimeter wave frequencies is first calculated with a harmonic balance based model. A numerical analysis method is developed to analyze the high-frequency resonant tunneling diode oscillator. The possible oscillation frequency and its output power of a resonant tunneling diode oscillator could be calculated easily with this high-frequency simulator. With the assistance of this developed analysis procedure, the high-frequency resonant tunneling diode oscillator design can become more efficient.

A Low-Power 2/5.8-GHz CMOS LC-VCO for Multi-band Wireless Communication Applications

A fully integrated dual-band LC voltage control oscillator designed in a 0.18-mum CMOS technology for 5.8-GHz/2.0-GHz wireless communication applications is described. The frequency band switching is accomplished with switched-inductor technique. The dual-band oscillator can be operated in 5.38~6.23 GHz and 1.78~2.07 GHz with 15% frequency tuning range. Two different inductors are used for the frequency band switching. Frequency tuning is implemented by varying the capacitance of a MOS varactor. The measured phase noise is -109 dBc/Hz @1 MHz and -112 dBc/Hz @1 MHz for frequency at 5.8 GHz and 2 GHz, respectively. This oscillator is fabricated in UMCs 0.18-mum one-poly-six-metal 1.8 V process. The power dissipation of this dual-band VCO is 11.7 and 9.3 mW for oscillation frequency of 2 GHz and 5.8 GHz, respectively

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35 µm CMOS high-frequency model to design a fully integrated 1 V, 5.2 GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50 Ω. The simulation results show that the amplifier provides a gain of 9.48 dB, a noise figure of 4.08 dB, and draws 13.4 mW from a 1 V supply. The S11 and S22 are both lower than −15 dB.

An Low Power Ultra-Wideband CMOS LNA for 3.1~8.2-GHz Wireless Receivers

This paper presents an ultra-wideband (UWB) 3.1~8.2-GHz low-noise amplifier design. Resistive shunt-feedback method is used to provide wideband input matching and low noise figure (NF). The cascade configuration is employed with the inductive source degeneration and an input three-section band-pass Chebyshev filter. The LNA operates at 1.5 Volt and consumes 16.2 mW. At 3.1~8.2-GHz, this LNA has NF of 3.6 dB, with input return loss of -12.155 dB, output return loss of -12.75 dB, and power gain of 11.43 dB. The circuit is designed with TSMC 0.18 mum single-poly-six-metal CMOS process

A Low-voltage low-power programmable 5 GHz frequency synthesizer in standard 0.18 µm CMOS process

A low-voltage programmable frequency synthesizer with 12.5  mW power consumption is designed for wireless communications. This synthesizer is implemented using Taiwan Semiconductor Manufacture Company (TSMC) 0.18 µm 1P6M triple-well technology, with an operating voltage of 1.5 volts, and an output frequency range from 4.58 GHz to 5.20 GHz. Based on the structure of phase-locked loop, we developed this fully integrated frequency synthesizer using the phase-locked (PLL) loop structure, consisting of a phase/frequency detector (PFD), a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider. The PFD is composed of dynamic two-phase master-slave pass-transistor flip-flops. Only single-edge clocks are used to minimize clock skew. To reduce the charge sharing and clock feed-through problems a novel charge pump structure is designed. A three-order low-pass filter is used to filter out the high-frequency alias of charge pump circuit. The voltage-controlled oscillator adopts a novel differential Colpitts oscillator structure to increase the oscillator frequency to 5 GHz. An injection-locked frequency divider is used in the PLL feedback path to reduce the overall power consumption.