Wanlong Chen

A supervised spiking time dependant plasticity network based on memristors

Synaptic plasticity has been widely assumed to be the mechanism behind memory and learning, in which, synapse has a critical role. As a newer biologic update rule to hebbian learning, spiking-time dependent plasticity (STDP) concerns on the temporal order of presynaptic spike and postsynaptic spike which will change the strength of, the connection site of neurons, synapse. In this paper a different way is shown to utilise the novel element memristors to implement a supervised STDP. Because the resistance of memristor depends on its past states, researchers are particularly interested in using such functionality to mimic synaptic connection. Furthermore, benefit from the nano size of memristors and its crossbar structure, large scale neural networks could be implemented. In this supervised STDP, each spike arrival will be assumed to leave a trace which decays exponentially and spikes interact under all-to-all interaction. Depending on the temporal order, memristor synapse will weaken or strengthen the connection of presynaptic neuron and postsynaptic neuron. The temporal all-to-all interaction is implemented during the simulation with training samples. We show that, by combining the memristors, a supervised STDP neural network can be built and learn from the temporal order of presynaptic spike and postsynaptic spike of the training samples.

2013 Special Issue: Adaptive Neuromorphic Architecture (ANA)

We designed Adaptive Neuromorphic Architecture (ANA) that self-adjusts its inherent parameters (for instance, the resonant frequency) naturally following the stimuli frequency. Such an architecture is required for brain-like engineered systems because some parameters of the stimuli (for instance, the stimuli frequency) are not known in advance. Such adaptivity comes from a circuit element with memory, namely mem-inductor or mem-capacitor (memristors sisters), which is history-dependent in its behavior. As a hardware model of biological systems, ANA can be used to adaptively reproduce the observed biological phenomena in amoebae.

The memristor-based associative learning network with retention loss

The memristor is an emerging device in nanotechnology, which provides nanoscale size, low power consumption and high density. It has been widely used in neural networks where memristors are utilised as synaptic weights (connection sites) between neurons. In particular, current research focuses on the spiking-time dependant plasticity (STDP) which is an important synaptic modification rule based on the timings of the pre- and postsynaptic spikes. It has been revealed that the memristor is intrinsically similar with a synapse and capable to mimic the long-term depression (LTD) and long-term potentiation (LTP) behaviours under the STDP rule. Further studies show that the associative learning can be mimicked by memristive neural networks through proper learning rules. However, such studies focus on demonstrating the process of building the association, which lacks the retention loss process of forgetting the association. In this paper, a rate-based term is proposed to improve the previous model, and therefore the retention loss process can be implemented in the given network. The results demonstrate that the network with the improved model can successfully reproduce the retention loss process meanwhile retaining the process of building the association.

The staircase memristor and its applications

Memristor is a newly emerged device in nano-technology that provides low power consumption as well as high density. In this paper, the staircase memristor which has multiple stable resistive states is modelled and exploited, and its possible applications are investigated. Comparing with the analog memristor model proposed by HP, the staircase memristor model shows a significant delayed-switching effect which yields a range of more or less discrete memristance values rather than continuous values. We present using the staircase memristor to produce staircase waveforms which can be used in testing circuit or sampling oscilloscope. Besides, staircase memristors are used in cellular neural network (CNN) circuits to represent the connection weights between CNN cells. Benefit from the simple structure, non-volatility and low power properties, the complexity and size of CNN circuits can be reduced.

An Omnipotent Memristor Model with Controllable Window Functions

Memristors are labelled as a significant candidate of building a better storage structure, higher capacity and more efficient performance. Research shows that the density of a memristor array could be 100 times higher compared to the dynamic random-access memory, hence it is possible to build a storage structure with high density. Tracing back to the year 1971, Prof. Chua firstly proposed the memristor as the fourth circuit element and defined it as memory-resistor, it is a new emerged passive device with two terminals that have the ability to respond to the history or past memory of the current that passes within it. We hereby, propose comprehensive numerical models based window functions. When the parameters of the models are varied, various dynamic behaviours can be obtained and discussed.

Memristor content addressable memory

Content addressable memory is a novel storage device that can save data in its cells, which could be read, written and searched on the basis of their contents. This paper presents Memristor content addressable memory (M-CAM) structures that are formed of M-CAM cells, which compare searched data and stored data then give a cell output signal to be kept in its comparator. After the comparison in each cell, reading is enabled at each row of all comparators. The current of each row could be measured, if some comparators are high resistance (0) in a row, the current of that row could be lower than the current from another row where all comparators are low resistance (1), which means the corresponding row is a match. The main emphasis of this paper is to highlight the process of the M-CAM comparison and how to get the match entry. Our experimental results show that M-CAM is able to not only query accurately, but also fuzzy lookup through setting the memristor off-to-on resistance ratio.

An Extension of Hard Switching Memristor Model

Memristor was initially introduced by Professor Leon Chua in 1971 as the fourth passive fundamental circuit element. In this chapter, we revise and extend the hard switching memristor model, that is developed based on the HP’s memristor model. This model matches most of the memristor characteristics such as the pinched hysteresis loops (the fingerprint of memristive devices). Different materials of memristive devices could require different memristor models, which are sufficiently accurate and easily to do their simulations . The hard switching memristor model could be fit to specific materials of memristive devices and particular memristive systems. In some cases, this model is more reliable and flexible than the existing models of memristive devices.

A new memristor model for content addressable memory

Memristor is an emerging topic that has experienced a great development in the last few years. The concept of memristor was introduced as the fourth fundamental circuit element by Prof. Chua in the year 1971. A memristor could be one kind of electronic devices of novel nano-scale structures, which could be used in many applications, such as associative memories and neural networks. Among the emerging nano-technologies, memristors have become a very promising candidate because of its shorter switching time, higher capacity and lower power consumption. In this paper, we introduce that a new window function can be used to model the memristor based content addressable memory. Different memristive applications may require different memristor models, which are sufficiently accurate and simple for computing. This model could fit specific chemical materials in content addressable memory. In some cases, this model is more authentic and flexible than those existing memristor models for content addressable memory.