Warren Rosen

An autonomous articulating desktop robot for proctoring remote online examinations

In this paper we describe a new low-cost, autonomous desktop robot for proctoring examinations in online/distance learning courses. The robot is attached to the students computer via a USB port and monitors the examination environment using a webcam that articulates in both altitude and azimuth together with an array of acoustic sensors that provides audio directionality. The examination may be monitored in real time by a live proctor via the Internet or the data may be recorded for future review. Authentication of the identity of the test taker is accomplished using the webcam and simple, reliable ear recognition techniques. This eliminates the need for expensive digital fingerprint hardware.

A novel switch architecture for high-performance computing and signal processing networks

This work describes low-latency switch architecture for high performance packet-switched networks. The switch architecture is a combination of input buffers capable of avoiding head-of-line blocking and an internal switch interconnect capable of allowing different input ports to access a single output port simultaneously. The switch was designed for the RapidIO protocol, but provides improved performance in other switched fabrics as well. OPNET Modeler was used to develop models of the proposed switch architecture and to evaluate the performance of the switch for three different network topologies. Models of two standard switch architectures were also developed and simulated for comparison.

FAULT TOLERANCE IN AUTONOMOUS ACOUSTIC ARRAYS

Abstract The problem of fault tolerance in autonomous disposable fiber-optic-based acoustic arrays is considered. The principal source of failures over relatively short mission times is node outage due to battery run-down resulting in possible network failure, degradation in the beam power pattern, and possible loss of critical processing elements. Network integrity in the presence of node failures requires an optical bypass capable of bypassing several adjacent failed nodes. The effect of node failure on the beam power pattern is principally in the side lobes rather than in the main beam, and is amenable to relatively simple solutions for the case of failures near the ends of the array, but failures near the center are more intractable. The loss of critical processing elements can be dealt with by distributing the processing load over processing elements located in each telemetry node of the network, thereby turning the array into a distributed parallel computer.

An Internet-Based Quality Control Laboratory via Integration of Remote Robotic Operation and Nondestructive Ultrasound Evaluation

This paper discusses the integration of a remote robot laboratory with nondestructive ultrasound evaluation (NDE) experiments. A remotely automated quality inspection system is designed to analyze dimensions as well as detect internal flaws of parts via an Internet-based NDE system. The remote quality inspection system includes: Internet controllable robot via Ethernet connection, multiple Web-cameras, Ultrasonic Automatic Flaw Detector, LabVIEW module, and computers with Internet access capable of remote connection. The uniqueness of the project lies in making this process Internet-based and remote robot operated. An Internet-based procedure such as the one we are developing will allow industrial companies involved in NDE procedures to increase productivity and profits by allowing an employee to monitor multiple operations over the Internet without having to be at a specified location. In addition, the utilization of remotely controlled robots for educational purposes is expected to increase the degree of immersive presence of the students engaging in such Internet-based laboratory exercises as well as the level of online interactivity between the faculty and students.Copyright

A novel technique for upgrading the performance of FPGA-based legacy systems

Field Programmable Gate Arrays are frequently used in avionics signal processing applications due to their potential for substantial processing speedup. FPGAs can be particularly valuable in DSP applications because these tend to be data flow type problems. However, many systems employ FPGAs that are older and offer lower performance and fewer resources, making them difficult to upgrade as more powerful and processing-intensive algorithms become available. This problem is exacerbated by the fact that the process of translating all or part of a complex application to an FPGA is complicated, time-consuming, and prone to error, and the result often does not represent the optimum design in terms of performance, size, power consumption, and accuracy. As a result, a large, complex application may not fit on a legacy system or meet critical timing requirements. Commercially available automated design tools cannot guarantee that they represent the most optimal solution. In this paper we describe a new approach to automated FPGA hardware design that guarantees optimized hardware in terms of speed, power, area, or any combination of these characteristics while substantially decreasing design time. The approach also guarantees the correctness of the design in terms of the original algorithm, which may speed any required certification or recertification.