Wayne H. Woods

A new on-wafer de-embedding technique for on-chip rf transmission line interconnect characterization

Absfracf This paper introduces a new de-embedding method for on-chip RF transmission line characterization. The new technique allows subtraction of pad parasitics based on measurements of only two LI=L and Lz=N.L (N being a discrete number) long transmission lines with attached measurement pads. No dummy “open”, “short” and “thru” devices are required. The new method has also been extended for the case when Lz#N.L, and only L,, L2 and AL= L,-L, long interconnects with attached pads are available on the test wafer. The proposed methodology has been compared with several well-known de-embedding approaches (“thru”, “open-short” aed “short-open“) and with simulation results from the industry standard electromagnetic solver (lE3D) for de-embedding of on-chip interconnects at frequencies up to 70GHz. Index Terms -Transmission Line interconnect, on-wafer measurement, S-parameters, de-embedding.

CMOS millimeter wave phase shifter based on tunable transmission lines

This paper presents a tunable transmission line (t-line) structure, featuring independent control of line inductance and capacitance. The t-line provides variable delay while maintaining relatively constant characteristic impedance using direct digital control through FET switches. As an application of this original structure, a 60 GHz RF-phase shifter for phased-array applications is implemented in a 32 nm SOI process attaining state-of-the-art performance. Measured data from two phase shifter variants at 60 GHz showed phase changes of 175° and 185°, S21 losses of 3.5-7.1 dB and 6.1-7.6 dB, RMS phase errors of 2° and 3.2°, and areas of 0.073 mm2 and 0.099 mm2 respectively.

Novel low-cost on-chip CPW slow-wave structure for compact RF components and mm-wave applications

In this paper, an ideal slow wave coplanar waveguide (CPW) structures with low losses, moderate impedance and CMOS fabrication technology have been developed. The slow wave CPW transmission line structures were achieved through IBM 0.13 mum technology with multi-layer metals. The CPW were implemented with narrower signal line or wider separation between signal and ground plane to increase the inductance per unit length, while metal strips on another metal layers cross under/above the CPW lines, which are orthogonal to signal propagation direction. Losses reduction using via bars to increase the thickness of the signal metal layer, structures with metal strip options (above, under and both CPW) to increase the capacitance per unit length of the CPW and provide more flexibility for the proposed structure, effect of the metal strips pitch are also discussed. The slow wave structure discussed in this paper can shrink the side dimension of the mm-wave passive components by up to 35%.

Wideband on-chip RF MEMS switches in a BiCMOS technology for 60 GHz applications

In this paper, an on-chip RF MEMS capacitive switch is designed and simulated with a 0.13 mum IBM SiGe BiCMOS technology for the first time. Mechanical and electrical design of the high frequency switch are discussed in this paper. Special consideration to improve Con/Coff ratio of the switch is used with multi metal layers configuration. The switch is designed for 60 GHz wireless applications, the results show that the switch has the insertion loss is less than 0.2 dB when the switch is off, while the isolation loss is larger than 15 dB when the switch is on over the frequency from 40 to 70 GHz. The calculated pull-in voltage of the switch is only about 10 volts, the switch is compact comparing with the reported PIN diode RF switch and has the membrane dimension of 10 mum x 240 mum.

Novel on-chip high performance slow wave structure using discontinuous microstrip lines and multi-layer ground for compact millimeter wave applications

In this paper, a novel on chip slow wave structure is developed. It is built with discontinuous microstrip steps, the discontinuous line is made by placing a wide and short line and a narrow and short line in turn and the step discontinuity provides with additional inductance and capacitance. The slow wave transmission line structures were achieved through IBM 45 nm technology with multi-layer metals. Simulated and measured results for slow wave transmission line are provided in the paper for design with different characteristics impedances. Results have shown that the inductance per unit length and capacitance per unit length of the line increased about 50% compared with the conventional transmission line structure. In addition, the length effect of the wide and narrow signal sections is thoroughly studied and results have shown that the smaller the pitch, the better the slow wave effect which agrees with [7] very well. A 75 GHz Branchline coupler built with the slow wave transmission lines has also been designed, and the coupler is 70% smaller than the conventional design.

Silicon-chip single and coupled coplanar transmission line measurements and model verification up to 50GHz

Silicon technology on-chip single and coupled coplanar transmission lines have been measured on wafer up to 50 GHz. De-embedding was performed using various methods including the L-2L technique [1,2] by measuring two transmission lines of original and double length. A novel approach has been used for the measurement of the coupled structures using conventional two port VNA. Results are investigated both in S-parameter format and in gamma-Zo format, and compared with EM solver and the parametric IBM coplanar T-line device models discussed elsewhere [3,4] which are available in IBM CMOS and SiGe technology design kits. A comparison with RC model shows the limits of RC model validity, in frequency domain.

Novel on-chip variable delay transmission line with fixed characteristic impedance

On-chip electronically controllable delay elements are often used in RF designs such as phased array antenna systems. This paper presents a novel on-chip variable delay transmission line structure with fixed characteristic impedance. EM simulations show a delay change of 15.6 % is possible while the characteristic impedance of the novel transmission line varies a maximum of 3.7% from the 50 Ω target between two possible delay states.

Novel on-chip Through-Silicon-Via Wilkinson power divider

On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and good matching in both signal phase and amplitude at the two outputs.

Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides

This paper presents a new on-chip transmission line interconnect structure which offers the potential of superior return and insertion loss characteristics compared to the equivalent standard transmission line device. Conventional on-chip coplanar waveguides (CPW) and differential pairs are routed in a single metal layer in the chips metal-dielectric stack. The vertically stacked coplanar waveguide (PW) transmission lines presented here consist of metal lines on multiple metal levels connected by continuous via bars. The additional cross-sectional area of the VCPW topology decreases interconnect resistance while the increased effective device thickness increases capacitance to neighboring ground return lines leading to a characteristics impedance reduction.

An adaptive body-bias low voltage low power LC VCO

A novel LC VCO employing an adaptive body-bias is proposed for low power and low voltage high performance signal generation. By using the adaptive body-bias technique, the threshold voltage of the cross-coupled pair is reduced, and meanwhile the effective source-to-drain voltage and oscillation amplitude are increased, which improves the phase noise. In addition, the back-gate capacitances from the cross-coupled pair are used for frequency tuning which avoids quality factor deteriorations resulted from using extra tuning capacitance. In a standard 65nm CMOS process with a 0.4-V power supply, the proposed VCO achieves FOM of 189.8 with a phase noise of −122.5 dBc/Hz at 10MHz offset when operating at 24.25 GHz. The power consumption of the VCO is 0.94 mW.