Wayne Wei-Ming Dai

Routability of a rubber-band sketch

The SURF routing system employs a grid-less flexible routing topology called the rubber-band sketch, where each wire is treated as a rubber-band. One of the features of the SURF system is to provide an efficient routability test for this rubber-band topology. This paper presents the key concepts and necessary algorithms to perform this rou tability test.

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution

Power dissipated in clock distribution is a major source of total system power dissipation. Instead of increasing wire widths or lengths to reduce skew which results in increased power dissipation, we use a balanced buffer insertion scheme to partition a large clock tree into a number of small subtrees. Because asymmetric loads and wire width variations in small subtrees induce very small skew, minimal wire widths are used. This results in minimal wiring capacitance and dynamic power dissipation. Then the buffer sizing problem is formulated as a constrained optimization problem: minimize power subject to tolerable skew constraints. To minimize skew caused by device parameter variations from die to die, PMOS and NMOS devices in buffers are separately sized. Substantial power reduction is achieved while skews are kept at satisfiable values under all process conditions.

Useful-skew clock routing with gate sizing for low power design

Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skew may allow a larger timing budget for gate sizing. We construct a useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes form the feasible solution space of our problem. We use a merging segment perturbation procedure and a simulated annealing approach to explore various tree configurations. This is complemented by a bi-partitioning heuristic to generate appropriate connection topology and take advantage of useful skews. Experimental results have shown 11% to 22% total power reduction over previous methods of clock routing with zero-skew or single fixed skew bound and separately sizing logic gates.

Rubber band routing and dynamic data representation

A novel methodology and efficient algorithms are presented for performance driven routing based on computational geometry. A dynamic data representation using constrained triangulation is the key to achieving the efficient routability testing and incremental updating of topological routing. Variable width, variable spacing, evenly distributed spacing and thermal via insertion are used to handle crosstalk, switching noise, and thermal resistance problems.<<ETX>>

Topological routing in SURF: Generating a rubber-band sketch

A multi-layer topological router for generating rubberband sketches is described. The router uses hierarchical togdown partitioning to perform global routing for all nets simultaneously. I t combines this with successive refinement to help correct mistakes made before more detailed local information is discovered. Layer assignment is performed during the partitioning process to generate routing that has fewer vias and is not restricted to one-layer one-direction. The local router uses a region connectivity graph to generate shortest-path rubber-band routing.

Efficient three-dimensional extraction based on static and full-wave layered Green's functions

In tegral equation approaches based on layered media Greens functions are often used to extract models of integrated circuit structures. The primary advan tage of these approaches over equiv alen t-sourcebased schemes is the dramatic reduction in problem size. When combined with an SVD-accelerated sc heme for the solution of the associated dense linear system, this leads to a substantial speedup. In this paper we deriv e and solve for these multila yered 3D Greens functions using a transmission line circuit analog. A generalized image method for an arbitrary number of layers is presen ted. This method is rapidly con vergen t for near-field in teractions. F or the far field, a Chebyshev interpolation approach is adopted, where a database is precomputed (using a Fast Hankel T ransform) and stored. The combination of these tw o approaches leads to an extremely efficient scheme for the generation of Greens functions. We combine the SVD-accelerated integral equation solver IES3 with the multila yered Greens function approach, apply it to the extraction of IC parasitics and passive components, and we demonstrate its speed, accuracy and versatility via a number of examples.

SURF: rubber-band routing system for multichip modules

Current PCB (printed circuit board)-based routing tools cannot meet the performance and cost constraints presented by todays packaging technologies, including thin-film multichip modules. The authors describe SURF, a routing system designed specifically to meet these challenges. The strength of the SURF system comes from its extremely flexible rubber-band data representation. The rubber-band model is an ideal framework for performance-driven and cost-driven routing and naturally supports rectilinear, octilinear, and all-angle wiring patterns: one-and-a-half-layer routing; even wiring distribution; and powerful manual editing. The integrated spoke-based design-rule-checking/enforcement mechanism supports an incremental design style. As objects are moved or wires are resized, the wires are adjusted incrementally so that they maintain the same wiring topology. By working in the topological domain instead of the geometrical one, the designer can focus on higher-level design issues while the tool handles the precise geometrical details.<<ETX>>

S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function

A Scattering-Parameters (S-Parameters) based macromodel of distributed-lumped networks is presented. The networks can include capacitive cutsets, inductive loops, RLC meshes, and lossy transmission lines. An efficient network reduction algorithm is developed to reduce the original network into a network containing one multiport component together with the sources and loads of interest. The S-Parameters of the circuit components are approximated by Taylor series to simplify the reduction process. Exponentially Decayed Polynomial Function (EDPF) approximation is used to derive the macromodel, the higher accuracy can be obtained by selecting time constant according to an error criterion. The macromodel is always stable for a stable system and very flexible that the accuracy of the model can be controlled by adjusting the order of approximation. The experimental results indicate that our model can approach the accuracy of SPICE with one or two order less computing time.

Performance driven layout of thin-film substrates for multichip modules

The author addresses some of the problems encountered in propagating high-speed signals on lossy transmission lines of thin-film substrates for multichip modules. With the flexibility of rubber-band routing and the efficiency of a dynamic data representation based on constrained Delaunay triangulation, lossy and unterminated transmission lines can be generated that successfully propagate high speed signals. A substrate layout system, named SURF, is being developed for thin-film multichip module (MCM) substrate design.<<ETX>>

Chip Parasitic Extraction And Signal Integrity Verification

It was projected by the National Technology Roadmap for Semiconductors that by the year 1998 the feature size will shrink to 0.25pm and the chips may contain as many as 28 million transistors. As the width of wires shrinks, resistance increases more rapidly than capacitance decreases. As the result, interconnect contributes 50% of total delay in 0.35pm technology and is expected to contribute up to 70% in 0.25pm. Interconnect delay on chip dominates the gate delay. Large height to width ratio, 2:l in 1998 and 2.5:l in 2001, and many interconnect layers, 5-8 in 1998 and 8-10 in 2001, make lateral coupling increasingly more significant than coupling to ground. Cross talk not only causes a wrong logic result on one particular clock cycle, but also leads to a different timing behavior of neighboring lines. Delay cannot be calculated accurately without taking cross talk into account. Not to mention conformal dielectrics and non-orthogonal conductor cross sections. The above technology shift calls for 3D parasitic extraction. However, it is prohibitively expensive to extract every net in 3D; in fact, it is not necessary to do so. Before presenting the multi-tiered extraction methodology, I will first classify various extraction methodologies. According to degree of simplification made, various extraction methodologies fall into three categories: 2D, Quasi-3D or 2 iD, and 3D parasitic extraction. 2D parasitic extraction ignores all three dimensional details and assumes the geometries being modeled are uniform in one dimension, usually the signal propaga-