Wei Dou

Flexible protonic/electronic coupled neuron transistors self-assembled on paper substrates for logic applications

Flexible organic/inorganic hybrid and proton/electron coupled neuron transistors are self-assembled on paper substrates at room temperature. Solution-processed chitosan-based proton conductor gate dielectrics show a high electric-double-layer specific gate capacitance, which is favorable for low voltage portable application. High performance logic operations are realized on such flexible neuron transistors depending on the operation modes, i.e., “OR” logic for enhancement-mode device and “AND” logic for depletion-mode device. Proton/electron interfacial coupling in chitosan-gated neuron transistors is promising for the biological and sensing applications.

Junctionless Flexible Oxide-Based Thin-Film Transistors on Paper Substrates

Junctionless flexible oxide-based electric-double-layer thin-film transistors (TFTs) are fabricated on paper substrates at room temperature. Channel and source/drain electrodes are realized by an indium-tin-oxide (ITO) film without any source/drain junction. Effective field-effect modulation of drain current can be obtained when the thickness of the top ITO film is decreased to 20 nm. These junctionless paper TFTs show a good device performance with a small subthreshold swing of 0.21 V/dec and a large on/off ratio of 2 ×106. Such junctionless paper TFTs can provide a new opportunity for flexible paper electronics and low-cost portable-sensor applications.

Junctionless in-plane-gate transparent thin-film transistors

Junctionless transparent electric-double-layer thin-film transistors with an in-plane-gate figure are fabricated on glass substrates at room temperature. The unique feature of such junctionless transistors is that the channel and source/drain electrodes are the same thin indium-tin-oxide film without any source/drain junction. Effective field-effect modulation of drain current can be obtained when the indium-tin-oxide thickness is reduced to 20 nm. Such junctionless transparent thin-film transistors exhibit a good electrical performance with a small subthreshold swing ( 106), respectively. A serial-capacitor model is proposed to understand the operation mechanism.

In-plane-gate indium-tin-oxide thin-film transistors self-assembled on paper substrates

Oxide-based thin-film transistors (TFTs) with in-plane gate structure are self-assembled on paper substrates at room temperature by using only one nickel shadow mask. Indium-tin-oxide (ITO) channel and ITO electrodes (gate, source, and drain) can be deposited simultaneously without precise photolithography and alignment process. The equivalent field-effect mobility, subthreshold swing, and on/off ratio of such paper TFTs are estimated to be 22.4 cm2/V s, 192 mV/decade, and 8×105, respectively. A model based on two capacitors in series is proposed to further understand the operation mechanism.

Flexible Dual-Gate Oxide TFTs Gated by Chitosan Film on Paper Substrates

Low-voltage flexible dual-gate indium-tin-oxide-based thin-film transistors (TFTs) are self-assembled on SiO₂-covered paper substrates by one shadow mask diffraction method. Solution-processed chitosan gate dielectric films have a large gate specific capacitance (5.8 μF/cm²) due to the electric-double-layer effect. The subthreshold swing, drain-current on/off ratio, and field-effect mobility are estimated to be 80 mV/dec, 4 ×10⁶, and 9.3 cm²/V·s, respectively. Low-voltage operation mechanism and threshold voltage modulation of such dual-gate paper TFTs are investigated.

Laser directly written junctionless in-plane-gate neuron thin film transistors with AND logic function

Junctionless oxide-based neuron thin-film transistors with in-plane-gate structure are fabricated at room temperature by a laser scribing process. The neuron transistors are composed of a bottom indium-tin-oxide floating gate and multiples of in-plane control gates. The control gates, coupling with the floating gate, control the “on” and “off” of the transistor. Effective field-effect modulation of the drain current has been realized. AND logic is demonstrated on a dual in-plane gate neuron transistor. The developed laser scribing technology is highly desirable in terms of the fabrication of high performance neuron transistors with low-cost.

Low-Voltage Oxide-Based Electric-Double-Layer TFTs Gated by Stacked

Low-voltage oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by stacked SiO2 electrolyte/chitosan proton-conductor hybrid dielectric have been fabricated on glass substrates at room temperature. Such EDL TFTs exhibit a saturation mobility (μsat) of 7.8 cm2 V-1 s-1, a subthreshold swing (S) of 100 mV/decade, a drain current on/off ratio (Ion/off) of 7.8 × 105, and a threshold voltage (Vth) of -0.48 V. After aging for one month in air ambient without surface passivation, such device shows μsat of 3.5 cm2 V-1 s-1, Ion/off of 1.2 × 105, and S of 120 mV/decade. Control experiments demonstrate that devices gated by stacked SiO2 electrolyte/chitosan hybrid dielectrics show improved stability compared with TFTs gated by single chitosan or single SiO2 electrolyte gate dielectric.

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Threshold voltage (Vth) instability and surface passivation effect of transparent indium-zinc-oxide electric-double-layer thin-film transistors (TFTs) are investigated. Unpassivated devices show a large negative threshold voltage shift of 0.68 V in the beginning of light-illuminated negative gate bias stress. Under longer time stress, anomalous positive Vth shifts are observed for both unpassivated and passivated TFTs, which is due to the mobile ions drifting in the SiO2-based solid-electrolyte gate dielectric. After surface passivation, the devices show neglectable negative Vth shifts of less than 0.1 V due to the protection of channel against the photodesorption of adsorbed oxygen ions.

Electrolyte/Chitosan Hybrid Dielectrics

Low-voltage electric-double-layer (EDL) thin-fllm transistors (TFTs) have been fabricated on paper substrates at room temperature. The devices operated in depletion mode, and the resistivity of the Indium-Tin-Oxide (ITO) channel layer is measured to be 24 Ω · cm. An SiO₂ film deposited by plasma enhanced chemical-vapor deposition method is used as the buffer layer to improve the smoothness of the paper substrate. TFTs on the SiO₂-covered paper substrates show a saturation filed-effect mobility of 14.6 cm²V^-1s^-1, a subthreshold swing of 100 mV/dec, and a drain-current on/off ratio of 1.5 × 10⁶, which are much better than that of the devices on bare paper substrates. Such EDL TFTs on paper substrates with an SiO₂ buffer layer have potential application in portable sensors.

Anomalous Threshold Voltage Shift and Surface Passivation of Transparent Indium–Zinc–Oxide Electric-Double-Layer TFTs

Porous inorganic dielectrics provide nanochannels for ion transportation, which is favorable for electric-double-layer (EDL) formation. 1% CaCl2-treated porous SiO2 shows an increased EDL specific capacitance of ~4.2 µF/cm2. Low-voltage (1.0 V) indium–tin-oxide-based homojunction transistors gated by such a composite solid electrolyte are fabricated and characterized. After aging for one month in air ambient without surface passivation, such a device shows an equivalent field-effect mobility of 13 cm2 V-1 s-1, a current on/off ratio of 1.0×106, and a subthreshold swing of 80 mV/decade. Control experiment results demonstrate that the CaCl2 treatment can improve the stability of the EDL transistors.