Wei-Ting Kary Chien

Some practical considerations for effective and efficient wafer-level reliability control

In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cases are discussed regarding the suitable sampling plan and test structures. These studies are to improve WLRC effectiveness and efficiency, to diagnose reliability concerns, to expedite WLRC failure analyses when out-of-control, and, thus, to facilitate WLRC lot dispositions.

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

Abstract This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH4) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.

Fast WLRC applications in foundry fabrication

New reliability test methods and structures are needed and applied in advanced microelectronic fabrication. This work provides in-depth discussions on the double-point gate oxide integrity (GOI) test, fast I-ramp electromigration (EM) test, and an innovative test pattern to verify the probe contact resistance (PCR) and to improve WLRC (wafer level reliability control) test effectiveness, accuracy, and stability.

Practical WLRC methodology & applications in a wafer foundry

As the product life cycle shrinks, qualification needs to be completed in a much shorter time. This makes wafer level reliability (WLR) an important tool, enabling results to be obtained in a much shorter time. The two key issues for WLR are to guarantee the same failure mechanisms as conventional package-level reliability (PLR) and to maintain a statistically acceptable correlation (in terms of parameter estimation, lifetime projections and trend). We report the correlation of WLR and PLR tests and present WLR control (WLRC) methodology to ensure in-line reliability/process stability and to assist new technology development. We also present WLRC cases/plots/models, which show the benefits of a special control chart and principal component analysis (PCA). Apart from its use for in-line monitoring, by suitably designing the test structures and choosing the fail criteria, we also apply WLRC as a quick assessment of process/tool change qualification. WLRC can be embedded in the wafer acceptance test (WAT). We show how to use WLRC data to formulate reliability-WAT-yield models to facilitate yield improvement and reliability optimization.

Impact of pin configuration in IV characterization on ESD failure analysis

During ESD (Electro-Static Discharge) tests, IV curves are measured before and after ESD stress to judge the ESD protection circuit performance. In this paper, we report that the judgment in this way may be misleading if the pin configuration of the power supply pins or control pins are not well defined. Experiments & analysis are illustrated on configurations of: 1) Vss and Vdd pins, 2) Vdd pins from multiple power domains. We recommended that industry standards define the procedure on IV curve measurement and pin configurations as guidelines for ESD tests.

A cost-effective wafer-level reliability test system for integrated circuit makers

Wafer-level reliability (WLR) testing receives much attention and becomes a major tool for process reliability qualification and in-line monitoring because WLR can provide real-time results for timely improvements. This in-situ test capability is greatly attributed to an automatic parametric tester for sample handling and data collection/analysis. This paper presents a cost-effective WLR test system for a semiconductor maker (an IDM as well as a foundry). The proposed system consists of flexible and extensible algorithm generation, which helps realize low-cost WLR solutions. The key features of our proposed system include cost-effective instrumentation (i.e., an Agilent 4156C parameter analyzer, a semi-auto, and thermal CASCADE 12751 wafer prober, a pulse generator, and a switching matrix) and the software for interface control and data analysis. Compared with the corresponding automatic test equipment (ATE), our system is capable of measuring electrical characteristics with higher accuracy and a wider temperature range. This leads to significant cost saving, much enhanced tool utilization, and improved flexibility. Its great extensibility is especially important for a wafer foundry, which often suffers test capacity shortage when numerous verifications and qualifications are to be done.

Highly effective low-k dielectric test structures and reliability assessment for 28NM technology node and beyond

Low-k/ultra-low-k dielectric is expected to have large-scale implementation in the manufacturing of modern advanced IC technology nodes. The reliability performance of a low-k dielectric must meet the given target lifetime based on semiconductor electrical requirements. Reliability test structures are specifically devised in this paper. We proposed a series of fundamental improvements on test structures in terms of practical applications. Our data shows that intrinsic reliability of the low-k dielectrics can be further optimized through the process tuning without the variation in k value.

Crystal defects analysis using nano-probe technologies

With the device size shrinking to deep sub-micron region, silicon crystal defects become critical to device parameters. It also brings FA (Failure Analysis) great challenges on timely and exactly identifying the defect by EFA (Electrical Failure Analysis) and PFA (Physical Failure Analysis) methods. In this paper, we report the FAs on the single bit failure of a 6T-SRAM using nano-probe technologies for electrical localization. PFA methods, such as SEM (Scanning Electron Microscope), TEM (Transmission Electron Microscope), and chemical etching were performed for failure visualization.