Wei-Zen Chen

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10 Gbps optical receiver analog front-end (AFE), includes a trans-impedance amplifier (TIA) and a limiting amplifier (LA), is fabricated using a 0.18 /spl mu/m CMOS technology. The receiver front-end provides a conversion gain up to 85 dB/spl Omega/ and -3 dB bandwidth of 7.6 GHz. The sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10/sup -12/ with 2/sup 31/-1 pseudo-random bits. 3D symmetric transformers are utilized in the AFE design for bandwidth enhancement.

A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-

This paper describes the design of a 10-Gb/s fully integrated CMOS optical receiver, which consists of a novel spatially-modulated photo detector (SMPD), a low-noise trans-impedance amplifier (TIA), and a post-limiting amplifier on a single chip. The bandwidth of proposed meshed SMPD can be boosted up to 6.9 GHz under a reverse-biased voltage of 14.2 V. The measured responsivity of the meshed SMPD is 29 mA/W as illuminated by 850-nm light source. To compensate the relatively low responsivity of on-chip CMOS photo detector (PD), a high-gain TIA with nested feedback and shunt peaking is proposed to achieve low-noise operation. The optical receiver is capable of delivering 25-kΩ conversion gain when driving 50-Ω output loads. For a PRBS test pattern of 27- 1, the 10-Gb/s optoelectronic integrated circuit (OEIC) has optical sensitivity of - 6 dBm at a bit-error rate (BER) of 10 -11. Implemented in a generic 0.18-μm CMOS technology, the chip area is 0.95 mm by 0.8 mm. The trans-impedance amplifier, post amplifier, and output buffer respectively drain 38 mW, 80 mW, and 27 mW from the 1.8-V supply.

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In this work, we propose the design and implementation of a 13.56 MHz GaN Class-E power amplifier, which takes into account transistor parasitic effects. The design uses the parasitic capacitance of the transistor to replace the charging capacitance, simplifying the circuit structure and obtaining a 93.6% efficiency at output power of 26.8 W. In addition, a wireless power transfer system using the proposed Class-E amplifier is demonstrated, achieving a 73.4% system efficiency when the power delivered to the load is 25.6 W.

CMOS Technology

A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 ¿s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm 2.

A 25.6 W 13.56 MHz wireless power transfer system with a 94% efficiency GaN Class-E power amplifier

This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 inVpp to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SiVIL) detector and adaptive analog equalizer. Implemented in a 0.18 mum CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.

A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabri- cated in a low-cost 0.35- m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed opera- tions in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 A. The input sensitivity of the receiver front-end is 16 A for 2.5-Gbps operation with bit-error rate less than , and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is m m.

A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mVpp to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mum CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm2.

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents novel three-dimensional (3-D) symmetric passive components, including inductors, transformers, and balun. Layout areas of these components are drastically reduced by 32% to 70%, while the symmetry of the input and the output ports is still maintained. The inductance mismatch in the 3-D transformer is less than 0.1%, and the coupling coefficient can be up to 0.77. The 3-D balun manifests less than 0.6-dB gain mismatch for 10-GHz range, and the phase error is less than 7deg from 1- to 10-GHz frequency range according to measurement results. Furthermore, the self-resonant frequency (fSR) of the proposed architecture is improved by 32% to 61% in contrast to their planar counterparts. On the other hand, the quality factor is degraded by less than 2 for the sake of using lower metal layers. The distributed capacitance model is utilized to validate their superiorities in fSR. All the devices are fabricated in a generic 0.18-mum CMOS process.

A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector

A fully integrated 10 Gbps optical receiver analog front-end (AFE), includes a trans-impedance amplifier (TIA) and a limiting amplifier (LA), is fabricated using a 0.18 /spl mu/m CMOS technology. The receiver front-end provides a conversion gain up to 85 dB/spl Omega/ and -3 dB bandwidth of 7.6 GHz. The sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10/sup -12/ with 2/sup 31/-1 pseudo-random bits. 3D symmetric transformers are utilized in the AFE design for bandwidth enhancement.

Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology

This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning range DCO incorporating variable inductor (VID) techniques. The variable inductor, consisting of a transformer and a variable resistor, is tunable by adjusting its resistor. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operation are achieved without sacrificing their operating frequencies. To verify the operation principles, the VCO and DCO are both fabricated in 90 nm CMOS technology. The tuning range of VCO is from 52.2 GHz to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about - 118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. It dissipates 8.7 mW from a 0.7-V supply, and the chip size is 0.28×0.36mm2. On the other hand, the DCO is capable of covering frequency range from 37.6 GHz to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10-MHz offset, and the output power is -11 dBm. The DCO core dissipates 19 mW from a 1.2-V supply. Chip size is 0.5×0.15mm2.