Weiguang Xie

Electronic Properties of MoS2–WS2 Heterostructures Synthesized with Two-Step Lateral Epitaxial Strategy

Formation of heterojunctions of transition metal dichalcogenides (TMDs) stimulates wide interest in new device physics and technology by tuning optical and electronic properties of TMDs. TMDs heterojunctions are of scientific and technological interest for exploration of next generation flexible electronics. Herein, we report on a two-step epitaxial ambient-pressure CVD technique to construct in-plane MoS2-WS2 heterostructures. The technique has the potential to artificially control the shape and structure of heterostructures or even to be more potentially extendable to growth of TMD superlattice than that of one-step CVD technique. Moreover, the unique MX2 heterostructure with monolayer MoS2 core wrapped by multilayer WS2 is obtained by the technique, which is entirely different from MX2 heterostructures synthesized by existing one-step CVD technique. Transmission electron microscopy, Raman and photoluminescence mapping studies reveal that the obtained heterostructure nanosheets clearly exhibit the modulated structural and optical properties. Electrical transport studies demonstrate that the special MoS2 (monolayer)/WS2 (multilayer) heterojunctions serve as intrinsic lateral p-n diodes and unambiguously show the photovoltaic effect. On the basis of this special heterostructure, depletion-layer width and built-in potential, as well as the built-in electric field distribution, are obtained by KPFM measurement, which are the essential parameters for TMD optoelectronic devices. With further development in future studies, this growth approach is envisaged to bring about a new growth platform for two-dimensional atomic crystals and to create unprecedented architectures therefor.

High‐Performance Graphene Devices on SiO2/Si Substrate Modified by Highly Ordered Self‐Assembled Monolayers

Graphene fi eld-effect transistors (GFETs) are considered promising devices as a result of graphene’s notably high mobility, fl exibility, and ultrathin nature. [ 1 , 2 ] Indeed, high mobility up to 200 000 cm 2 V − 1 s − 1 and extraordinarily large mean free length were observed in clean suspended graphene at 5 K. [ 3 ] Unfortunately, the applications of graphene are usually confi ned by a standard SiO 2 /Si substrate through charge transfer, adsorbates, and electron phonon scattering. [ 4–8 ] It is a common desire to search for high quality substrates to accommodate graphene devices where the deleterious effects of the substrate can be minimized and the high mobility achieved in free standing graphene can be largely preserved. This is crucial: i) to obtain high performance devices for electronic applications, ii) to reveal the intrinsic properties of graphene, and iii) to understand the mystery of scattering origins, and the charge transfer and transport mechanisms in graphene devices. The groups of Hong and Dean have pioneered the search for novel substrates by using epitaxial ferroelectric dielectric (Pb(Zr 0.2 Ti 0.8 )O 3 (PZT)) and hexagonal boron nitride (h-BN) substrates. [ 9 , 10 ] The charge carrier mobilities in graphene devices fabricated on these substrates are found to be 70 000 and 64 000 cm 2 V − 1 s − 1 at high carrier density, respectively. However, it is generally believed that utilization of surface/interface engineering to modify the existing commercially available substrates, for example, silicon wafers with thermally grown silicon dioxide, is more useful because of the convenient and mature production process, low leakage current, small surface roughness, best optical contrast (especially for a 300 nm thick SiO 2 layer), and low cost. Only a few research efforts following this strategy have been reported, among which the groups of Lafkioti and Liu found that suppression of unintentional substrate doping effects can be achieved by insertion of hydrophobic self-assembled layers (hexamethyldisilane,

Lateral Built‐In Potential of Monolayer MoS2–WS2 In‐Plane Heterostructures by a Shortcut Growth Strategy

Lateral WS2-MoS2 heterostructures are synthesized by a shortcut one-step growth recipe with low-cost and soluble salts. The 2D spatial distributions of the built-in potential and the related electric field of the lateral WS2-MoS2 heterostructure are quantitatively analyzed by scanning Kelvin probe force microscopy revealing the fundamental attributes of the lateral heterostructure devices.

Freestanding CNT–WO3 hybrid electrodes for flexible asymmetric supercapacitors

Freestanding carbon nanotube (CNT)–tungsten oxide (WO3) hybrid films as the negative electrode of asymmetric supercapacitors (ASCs) are synthesized via a facile vacuum filtration and a subsequent physical vapor deposition method. With pure CNT films as the paired positive electrodes, these flexible ASC devices have been fabricated to demonstrate excellent electrochemical performance. Their cyclic voltammetry curves barely change when the ASC device is flat, bent, or twisted. Their volumetric capacitance reaches a high value of 2.6 F cm−3 at a scan rate of 10 mV s−1. Due to the extended operating voltage of 1.4 V, the ASC device reaches a power density of 30.6 mW cm−3 and an energy density of 0.59 mW h cm−3. After 50 000 cycles, the capacitance retention of the ASC is still 75.8%, which shows its excellent stability and ultra-long lifetime. When these ASC devices are connected in series as power sources, a commercial blue light-emitting diode can be lighted up and a commercial mobile-phone can be charged. In short, the novel ASC device with perfect flexibility and stability can be applied as one of the most promising next-generation power supplies.

Low-Voltage Organic Field-Effect Transistors (OFETs) with Solution-Processed Metal-Oxide as Gate Dielectric

In this study, low-voltage copper phthalocyanine (CuPc)-based organic field-effect transistors (OFETs) are demonstrated utilizing solution-processed bilayer high-k metal-oxide (Al(2)O(y)/TiO(x)) as gate dielectric. The high-k metal-oxide bilayer is fabricated at low temperatures (< 200 °C) by a simple spin-coating technology and can be controlled as thin as 45 nm. The bilayer system exhibits a low leakage current density of less than 10(-5) A/cm(2) under bias voltage of 2 V, a very smooth surface with RMS of about 0.22 nm and an equivalent k value of 13.3. The obtained low-voltage CuPc based OFETs show high electric performance with high hole mobility of 0.06 cm(2)/(V s), threshold voltage of -0.5 V, on/off ration of 2 × 10(3) and a very small subthreshold slope of 160 mV/dec when operated at -1.5 V. Our study demonstrates a simple and robust approach that could be used to achieve low-voltage operation with solution-processed technique.

Graphene Based Non‐Volatile Memory Devices

With the continuous advance of modern electronics, the demand for non-volatile memory cells rapidly grows. As a promising material for post-silicon electronic applications, graphene non-volatile memory cells have received renewed interest due to its outstanding electronic and other physical properties. This research news briefly summarizes the recent progress in this area. Appealing research activities and technical trends are highlighted. Afterwards, requirements and aims of future graphene non-volatile memory cells that may possibly influence their commercialization are also discussed.

Device lifetime improvement of polymer-based bulk heterojunction solar cells by incorporating copper oxide layer at Al cathode

Organic solar cells are commonly susceptible to degradation in air. We present that insertion of a thin layer of thermally evaporated copper oxide (CuOx) between the organic active layer and the Al cathode can greatly extend the lifetime of P3HT:PCBM based bulk heterojunction solar cells. The performance can be further improved by applying an interfacial bilayer of CuOx/LiF. Our results suggest that the CuOx functions not only as a charge transport layer but also as a protection layer, which prevents formation of thick organic-Al interdiffusion area. This leads to a more air-resistive cathode/organic interface.

Nanoscale Insights into the Hydrogenation Process of Layered α-MoO3

The hydrogenation process of the layered α-MoO3 crystal was investigated on a nanoscale. At low hydrogen concentration, the hydrogenation can lead to formation of HxMoO3 without breaking the MoO3 atomic flat surface. For hydrogenation with high hydrogen concentration, hydrogen atoms accumulated along the <101> direction on the MoO3, which induced the formation of oxygen vacancy line defects. The injected hydrogen atoms acted as electron donors to increase electrical conductivity of the MoO3. Near-field optical measurements indicated that both of the HxMoO3 and oxygen vacancies were responsible for the coloration of the hydrogenated MoO3, with the latter contributing dominantly. On the other hand, diffusion of hydrogen atoms from the surface into the body of the MoO3 will encounter a surface diffusion energy barrier, which was for the first time measured to be around 80 meV. The energy barrier also sets an upper limit for the amount of hydrogen atoms that can be bound locally inside the MoO3 via hydrogenation. We believe that our findings has provided a clear picture of the hydrogenation mechanisms in layered transition-metal oxides, which will be helpful for control of their optoelectronic properties via hydrogenation.

Characteristics of a silicon nanowires/PEDOT:PSS heterojunction and its effect on the solar cell performance.

The interfacial energy-level alignment of a silicon nanowires (SiNWs)/PEDOT:PSS heterojunction is investigated using Kelvin probe force microscopy. The potential difference and electrical distribution in the junction are systematically revealed. When the PEDOT:PSS layer is covered at the bottom of the SiNW array, an abrupt junction is formed at the interface whose characteristics are mainly determined by the uniformly doped Si bulk. When the PEDOT:PSS layer is covered on the top, a hyperabrupt junction localized at the top of the SiNWs forms, and this characteristic depends on the surface properties of the SiNWs. Because the calculation shows that the absorption of light from the SiNWs and the Si bulk are equally important, the bottom-coverage structure leads to better position matching between the depletion and absorption area and therefore shows better photovoltaic performance. The dependence of JSC and VOC on the junction characteristic is discussed.

A low-temperature, solution-processed high-k dielectric for low-voltage, high-performance organic field-effect transistors (OFETs)

We report here a low-temperature, solution-processed high-k dielectric, which can be used effectively to achieve high-performance, low-voltage organic field-effect transistors (OFETs). A CuPc device based on the solution-processed dielectric possessed a mobility of 0.15cm 2 V ! 1 s ! 1 under a voltage of only ! 2V, which is more than one order of magnitude higher than that obtained on traditional 300nm SiO2 under ! 40V. Detailed studies by atomic force microscopy and grazing incidence x- ray diffraction reveal that the high performance can be attributed to the crystallized interconnected rod-like structure of CuPc molecules in the initial growth on ATO. Pentacene and rubrene single crystal FETs on the solution-processed dielectric also exhibit higher performance than those on 300nm SiO2. Our findings suggest that the low-temperature, solution-processed high-k dielectric can be a plausible choice for fabrication of high-performance low-voltage OFETS, and also provide some clues in designing effective high-k dielectrics.