Weileun Fang

Localized induction heating solder bonding for wafer level MEMS packaging

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus thin film materials would not be damaged. Moreover, the bond strength between silicon and silicon wafer was higher than 18 MPa. The step height of the feed-through wire (acting as the electrical feed-through of the bonded region) is sealed by the electroplated film. Thus, the flatness and roughness of the electroplated surface are recovered by the solder reflow, and the package for preventing water leakage can be achieved. The integration of the surface micromachined devices with the proposed packaging techniques was demonstrated.

On the thermal expansion coefficients of thin films

The coefficient of thermal expansion CTE is an important mechanical property for thin film materials. There are several problems that arise from the thermal expansion effect; for example, the mismatch of thermal expansion between the thin films and the underlying substrate may lead to residual stresses in the thin films. On the other hand, the thermal expansion effect can be exploited to drive microactuators. The CTEs of Al and Ti thin films were determined in the present study using the bilayer microcatilever technique. The contribution of this paper is to demonstrate the variation of the thin film CTE with the film thickness. The CTE of the Al thin film changes from 18.23= 10 y6 r8C to 29.97= 10 y6 r8C, when the film thickness increases from 0.3 to 1.7 mm. The CTE of the Ti thin film changes from 21.21= 10 y6 r8C to 9.04 = 10 y6 r8C, when the film thickness increases from 0.1 to 0.3 mm. Further, the concept that thin film CTE may be influenced by the defects in thin film materials is proposed. Thus, a desired thin film CTE can be obtained by tuning the film thickness as well as the deposition conditions. q 2000 Elsevier Science S.A. All rights reserved.

Implementation of a Monolithic Single Proof-Mass Tri-Axis Accelerometer Using CMOS-MEMS Technique

This paper presents a novel single proof-mass tri-axis capacitive type complementary metal oxide semiconductor-microelectromechanical system accelerometer to reduce the footprint of the chip. A serpentine out-of-plane (Z-axis) spring is designed to reduce cross-axis sensitivity. The tri-axis accelerometer has been successfully implemented using the TSMC 2P4M process and in-house postprocessing. The die size of this accelerometer chip containing the MEMS structure and sensing circuits is 1.78 × 1.38 mm, a reduction of nearly 50% in chip size. Within the measurement range of ~0.8 6G, the tri-axis accelerometer sensitivities (nonlinearity) of each direction are 0.53 mV/G (2.64%) for the X-axis, 0.28 mV/G (3.15%) for the Y-axis, and 0.2 mV/G (3.36%) for the Z-axis, respectively. In addition, the cross-axis sensitivities of these three axes range from 1% to 8.3% for the same measurement range. The noise floors in each direction are 120 mG/rtHz for the X-axis, 271 mG/rtHz for the Y-axis, and 357 mG/rtHz for the Z-axis.

A generalized CMOS-MEMS platform for micromechanical resonators monolithically integrated with circuits

A generalized foundry-oriented CMOS-MEMS platform well suited for integrated micromechanical resonators alongside IC amplifiers has been developed for commercial multi-user purpose and demonstrated with a fast turnaround time of only 3 months and a variety of design flexibilities for resonator applications. With this platform, different configurations of capacitively-transduced resonators monolithically integrated with their amplifier circuits, spanning frequencies from 500 kHz to 14.5 MHz, have been realized with resonator Q’s ranging between 700 and 3500. This platform, specifically featured with various configurations of structural materials, multi-dimensional displacements, different arrangements of mechanical boundary conditions, tiny supports of resonators, large transduction areas, well-defined anchors and performance enhancement scaling with IC fabrication technology, offers a variety of flexible design options targeted for sensor, timing reference, and RF applications. In addition, resonators consisting of metal-oxide composite structures fabricated by this platform offer an effective temperature compensation scheme for the first time in CMOS-MEMS resonators, showing TCf six times better than that of resonators merely made by CMOS metals. (Some figures in this article are in colour only in the electronic version)

Determining thermal expansion coefficients of thin films using micromachined cantilevers

Abstract In this research, the coefficient of thermal expansion (CTE) of thin films was studied through analytical and experimental approaches using micromachined beams. Both single layer and bilayer micromachined cantilevers (microcantilevers) were exploited in measuring the thermal expansion of the thin films. It was obtained that both single and bilayer micromachined cantilevers would exhibit an out of plane deflection after subjected to temperature changes. Thus the thermal expansion of thin film materials can be determined using optical interferometric techniques on these heat-deformed microcantilevers. The contributions of the proposed techniques are that they can be used to increase the sensitivity and accuracy of CTE measurements. Furthermore, the distribution of the thin film CTE across the entire substrate can also be determined through the proposed approaches. Since the microcantilever structure used in this study is very simple, both modeling and fabrication processes are simplified. Thus the proposed technique can be applied to supplement other techniques used in determining the CTE of thin films.

Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

Design and application of a metal wet-etching post-process for the improvement of CMOS-MEMS capacitive sensors

This study presents a process design methodology to improve the performance of a CMOS-MEMS gap-closing capacitive sensor. In addition to the standard CMOS process, the metal wet-etching approach is employed as the post-CMOS process to realize the present design. The dielectric layers of the CMOS process are exploited to form the main micro mechanical structures of the sensor. The metal layers of the CMOS process are used as the sensing electrodes and sacrificial layers. The advantages of the sensor design are as follows: (1) the parasitic capacitance is significantly reduced by the dielectric structure, (2) in-plane and out-of-plane sensing gaps can be reduced to increase the sensitivity, and (3) plate-type instead of comb-type out-of-plane sensing electrodes are available to increase the sensing electrode area. To demonstrate the feasibility of the present design, a three-axis capacitive CMOS-MEMS accelerometers chip is implemented and characterized. Measurements show that the sensitivities of accelerometers reach 11.5 mV G−1 (in the X-, Y-axes) and 7.8 mV G−1 (in the Z-axis), respectively, which are nearly one order larger than existing designs. Moreover, the detection of 10 mG excitation using the three-axis accelerometer is demonstrated for both in-plane and out-of-plane directions.

Flexible carbon nanotubes electrode for neural recording.

This paper demonstrates a novel flexible carbon nanotubes (CNTs) electrode array for neural recording. In this device, the CNTs electrode arrays are partially embedded into the flexible Parylene-C film using a batch microfabrication process. Through this fabrication process, the CNTs can be exposed to increase the total sensing area of an electrode. Thus, the flexible CNTs electrode of low impedance is realized. In application, the flexible CNTs electrode has been employed to record the neural signal of a crayfish nerve cord for in vitro recording. The measurements demonstrate the superior performance of the presented flexible CNTs electrode with low impedance (11.07 kohms at 1 kHz) and high peak-to-peak amplitude action potential (about 410 microV). In addition, the signal-to-noise ratio (SNR) of the presented flexible CNTs electrode is about 257, whereas the SNR of the reference (a pair of Teflon-coated silver wires) is only 79. The simultaneous recording of the flexible CNTs electrode array is also demonstrated. Moreover, the flexible CNTs electrode has been employed to successfully record the spontaneous spikes from the crayfish nerve cord. The amplitude of the spontaneous peak-to-peak response is about 25 microV.

Implementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration

This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si–glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructures is decreased and mismatch of coefficient of thermal expansion (CTE) is reduced. In applications, the glass reflow process together with the SOG micromachining processes were employed to implement the presented concept. Successful driving of the resonator through the silicon vias is demonstrated. The wafer-level hermetic packaging can be further achieved by anodic bonding of a Pyrex7740 wafer. Hermeticity of the packaged device performed by helium leak test satisfied MIL-STD-883E. The packaged SOG device is SMT (surface mount technology) compatible and ready for 3D microsystem integration.

Thermal Actuated Solid Tunable Lens

In this letter, the concept of driving tunable solid lens using microthermal actuator is presented. This microoptical device is composed of a flexible polydimethylsiloxane (PDMS) lens, silicon conducting ring, and silicon heater. The mismatching of coefficient of thermal expansion and stiffness between PDMS and silicon will lead to the deformation of polymer lens during heating, so as to further change its focal length. To demonstrate the feasibility of this approach, a microfabrication processes have been established to monolithically fabricate the present microoptical device. The typical experiment results show that the tunable focal length was up to 834 mum with an input current of 70 mA