Weize Xiong

Improvement of FinFET electrical characteristics by hydrogen annealing

Hydrogen anneal is used during FinFET processing to round off the corners of the silicon fins prior to gate oxidation and to smooth the surface of the fin sidewalls. This procedure greatly improves gate leakage and, in addition, reduces the width of the fins, resulting in a lower threshold voltage and improved drain-induced barrier lowering (DIBL) characteristics. Reduction of the leakage current by up to four orders of magnitude is obtained after edge rounding by hydrogen annealing. In addition, a 50% decrease of DIBL is observed, due to fin width reduction.

Quantum-mechanical effects in trigate SOI MOSFETs

A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.

Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility

In this letter, it is shown that for fin widths down to < 20 nm, strain can be retained in patterned strained-silicon-on-insulator (sSOI) films and is correlated to mobility enhancements observed in FinFET devices. NMOS FinFET mobility is improved by 60% and 30% for [110]/<110> and (100)/<100> fin surface/direction, respectively. Although PMOS FinFET mobility is degraded by 35% for [110]/<110> fins, it is enhanced by up to 30% for (100)/<100> fins. These results can be qualitatively explained using the bulk-Si piezoresistance coefficients.

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.

Body effect in tri- and pi-gate SOI MOSFETs

A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate.

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

A novel surface-potential based multi-gate FET (MG-FET) compact model has been developed for mixed-signal design applications. For the first time, a MG-FET model captures the effect of finite body doping on the electrical behavior of MG-FETs. A unique field penetration length model has been developed to model the short channel effects in MG-FETs. A multitude of physical effects such as poly-depletion effect and quantum-mechanical effect (QME) have been incorporated. The expressions for terminal currents and charges are co-continuous making the model suitable for mixed-signal design. The model has been verified extensively with TCAD and experimental data.

Radiation Dose Effects in Trigate SOI MOS Transistors

N-channel trigate SOI MOSFETs have been irradiated with 60 Co gamma rays at doses up to 6 Mrad(SiO2). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 mum. At 6 Mrad(SiO2), the current drive reduction in the same devices is 10% if VG=0 V during irradiation and 20% if VG=1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [<1 Mrad(SiO2)]. At higher doses, the usual mobility degradation caused by interface trap generation is observed

ESD Evaluation of the Emerging MuGFET Technology

ESD characteristics of fully depleted (FD) FinFET devices are presented and compared to planar structures manufactured in the same multiple-gate FET (MuGFET) technology. FinFET-type MOS devices in breakdown mode are found to show an unprecedented sensitivity to ESD stress, while planar devices and FinFET gated diodes perform reasonably and with I-V characteristics beneficial for ESD protection.

Design of FinFET SRAM Cells Using a Statistical Compact Model

A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.

Properties of Accumulation-Mode Multi-Gate Field-Effect Transistors

In this work, we analyze the conduction mechanisms and the electrical performance of intrinsic and doped accumulation-mode (AM) p-type, triple-gate silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFETs). Both long- and short-channel devices with different fin widths are investigated on the basis of experimental and simulation data. The analysis shows that for a small fin width, the threshold voltages associated with both body current and side channels in heavily doped devices coincide, thereby preventing the increase in leakage current caused by body conduction that is conventionally observed in planar AM fully-depleted (FD) SOI MOSFETs. Shortchannel effects (SCEs) are minimized in these devices owing to the good electrostatic control by the surrounding gate. The experimental data indicate that SCEs are comparable to those observed in inversion-mode (IM) devices with a gate length of 50 nm. This makes AM triple-gate (or more generally, multigate) MOSFETs interesting devices for digital applications.