Wen-Yew Liang

Design and Implementation of a Critical Speed-Based DVFS Mechanism for the Android Operating System

DVFS is an efficient energy saving technique for processors during program execution time. A critical speed-based DVFS mechanism that we have implemented on the Android operating system is introduced. Our studies indicate that due to memory accesses, decreasing the frequency may not always reduce the energy consumption. A critical speed is thus defined as the CPU frequency with which the energy consumption can be minimized. In our mechanism, a prediction equation based on the correlation of the memory access rate and the critical speed was constructed and used to choose a suitable frequency and voltage dynamically at run time. Our initial experiment results show that for real applications running on Android, the energy consumption can be effectively reduced.

A GPU-Based Simulation of Tsunami Propagation and Inundation

Tsunami simulation consists of fluid dynamics, numerical computations, and visualization techniques. Nonlinear shallow water equations are often used to model the tsunami propagation. By adding the friction slope to the conservation of momentum, it also can model the tsunami inundation. To solve these equations, we use the second order finite difference MacCormack method. Since it is a finite difference method, it brings the possibility to be parallelized. We use the parallelism provided by GPU to speed up the computations. By loading data as textures in GPU memory, the computation processes can be written as shader programs and the operations will be done by GPU in parallel. The results show that with the help of GPU, the simulation can get a significant improvement in the execution time for each of the computation steps.

GPU Acceleration of Tsunami Propagation Model

Tsunami propagation in shallow water zone is often modeled by the shallow water equations (also called Saint-Venant equations) that are derived from conservation of mass and conservation of momentum equations. Adding friction slope to the conservation of momentum equations enables the system to simulate the propagation over the coastal area. This means the system is also able to estimate inundation zone caused by the tsunami. Applying Neumann boundary condition and Hansen numerical filter bring more interesting complexities into the system. We solve the system using the two-step finite-difference MacCormack scheme which is potentially parallelizable. In this paper, we discuss the parallel implementation of the MacCormack scheme for the shallow water equations in modern graphics processing unit (GPU) architecture using NVIDIA CUDA technology. On a single Fermi-generation NVIDIA GPU C2050, we achieved 223x speedup with the result output at each time step over the original C code compiled with -O3 optimization flag. If the experiment only outputs the final time step result to the host, our CUDA implementation achieved around 818x speedup over its single-threaded CPU counterpart.

Vision-Based Finger Detection, Tracking, and Event Identification Techniques for Multi-Touch Sensing and Display Systems

This study presents efficient vision-based finger detection, tracking, and event identification techniques and a low-cost hardware framework for multi-touch sensing and display applications. The proposed approach uses a fast bright-blob segmentation process based on automatic multilevel histogram thresholding to extract the pixels of touch blobs obtained from scattered infrared lights captured by a video camera. The advantage of this automatic multilevel thresholding approach is its robustness and adaptability when dealing with various ambient lighting conditions and spurious infrared noises. To extract the connected components of these touch blobs, a connected-component analysis procedure is applied to the bright pixels acquired by the previous stage. After extracting the touch blobs from each of the captured image frames, a blob tracking and event recognition process analyzes the spatial and temporal information of these touch blobs from consecutive frames to determine the possible touch events and actions performed by users. This process also refines the detection results and corrects for errors and occlusions caused by noise and errors during the blob extraction process. The proposed blob tracking and touch event recognition process includes two phases. First, the phase of blob tracking associates the motion correspondence of blobs in succeeding frames by analyzing their spatial and temporal features. The touch event recognition process can identify meaningful touch events based on the motion information of touch blobs, such as finger moving, rotating, pressing, hovering, and clicking actions. Experimental results demonstrate that the proposed vision-based finger detection, tracking, and event identification system is feasible and effective for multi-touch sensing applications in various operational environments and conditions.

Low-complexity Gaussian normal basis multiplier over GF(2 m )

The elliptic curve cryptosystem (ECC) is very attractive for the use in portable devices because of the small key size. The finite field multiplication over GF(2 m ) is the most important arithmetic for performing the ECC. Portable devices usually have restricted computation power and memory resources. This work will present a simple method for designing a Gaussian normal basis (GNB) multiplier over GF(2 m ) needing only fewer computation power whereas keeping lower cost. The proposed Gaussian NB multiplier saves � 57% space complexity as compared with existing GNB multiplier.

Design of a dynamic distributed mobile computing environment

Many of the embedded systems have integrated the features of multimedia, networking, and mobility in a device. With the capability of wireless communication, mobile devices can be connected to share information, and even more, work together to accomplish a more complex job. In this paper, a novel distributed mobile computing model based on the concept of dynamic task group is proposed. Through this dynamic distributed mobile computing (Dynamic-DMC) model, computing resources can be added and removed dynamically according to the availability of the resources. An environment supporting the Dynamic-DMC model, called D2MCE, has also been implemented. In D2MCE, a shared memory abstraction layer is provided for the purpose of easy programming. An example D2MCE program is also given in this paper. The Dynamic-DMC model and the D2MCE implementation can also be used in traditional cluster computing. Initial result shows that the performance of D2MCE is acceptable.

A simulated annealing band selection approach for hyperspectral imagery

For hyperspectral imagery, greedy modular eigenspaces (GME) has been developed by clustering highly correlated hyperspectral bands into a smaller subset of band modules based on greedy algorithm. Instead of greedy paradigm as adopted in GME approach, this paper introduces a simulated annealing band selection (SABS) approach for hyperspectral imagery. SABS selects sets of non-correlated hyperspectral bands for hyperspectral images based on simulated annealing (SA) algorithm while utilizing the inherent separability of different classes in hyperspectral images to reduce dimensionality and further to effectively generate a unique simulated annealing module eigenspace (SAME) feature. The proposed SABS features: (1) avoiding the bias problems of transforming the information into linear combinations of bands as does the traditional principal components analysis (PCA); (2) selecting each band by a simple logical operation, call SAME feature scale uniformity transformation (SAME/FSUT), to include different classes into the most common feature clustered subset of bands; (3) providing a fast procedure to simultaneously select the most significant features according to SA scheme. The experimental results show that our proposed SABS approach is effective and can be used as an alternative to the existing band selection algorithms.

Energy efficient video decoding for the Android operating system

Dynamic voltage and frequency scaling (DVFS) is an effective technique for reducing power consumption. Due to the increasing popularity of multimedia applications for portable consumer electronic devices, the importance on reducing their power consumption becomes significant. This paper proposed a table-based DVFS mechanism for frame decoding that reduces the power consumption of a processor by exploiting the frame decoding complexity. A table-based DVFS predictor is used in the frame decoding prediction. This study was implemented in the Android operating system on an Intel PXA27x embedded platform. Experiment results showed that the energy consumption of decoding videos can be reduced from 9% to 17%, whereas the frame drop-rate is less than 3%.

A memory-aware energy saving algorithm with performance consideration for battery-enabled embedded systems

Dynamic voltage and frequency scaling is an important mechanism for reducing the energy consumption of a processor while tasks are running. Our studies indicated that the lowest energy consumption usually appears at some frequency other than the lowest frequency. In addition, there exists an inverse relationship between memory access rate and the frequency which can minimize the energy consumption. A correlation equation can thus be deduced from the relationship and used at task execution time to find a frequency which tends to minimize the energy consumption. In this paper, an energy saving DVFS algorithm based on the correlation equation is proposed. It maintains the performance at a reasonable level. The algorithm has been implemented on Linux as a user-space power manager. The experiment results show that our algorithm performed better than the commonly used Linux Ondemand DVFS algorithm, according to the energy-delay production metric.

Concurrent error detection in semi-systolic dual basis multiplier over GF(2 m ) using self-checking alternating logic

Multiplication is one of the most important finite field arithmetic operations in cryptographic computations. Recently, the attacks of fault-based cryptanalysis have been a critical threat to both symmetrical and asymmetrical cryptosystems. To prevent such kind of attacks, masking faulty signals and outputting only correct ciphers would be a feasible solution, especially suitable for finite field multiplication. Therefore a novel dual basis multiplier in GF(2m) with concurrent error detection capability using self-checking alternating logic is presented. The new self-checking alternating logic dual basis multiplier saves about 67% space complexity as compared with other existing dual basis multiplier with concurrent error detection capability that uses the parity checking method. The proposed dual basis multiplier takes almost as low as one extra clock cycle to achieve concurrent error detection capability. Furthermore, any existing faults in fault model are ensured to be detectable through at least one input in the authors’ proposed scheme.