Wenbiao Zhou

Performance analysis of wireless sensor network based on NS-2

The wireless sensor network is one new hot spot for both research and industry. Currently several communication protocols have been developed for wireless sensor network, including Zigbee, wirelessHART, ISA100.11a, WIA-PA, and so on. Most of these protocols are developed based on IEEE 802.15.4. IEEE 802.15.4 was designed for low-cost and low-power wireless network which provides MAC layer and physical layer specification. In this paper, the performance of IEEE802.15.4 is analyzed based on NS-2 simulator. According to the simulation results, Performance is analyzed for different application requirements, for example, the packet reception ratio over different sending interval time, the packed routing load over different sending interval time. etc.

Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

The carrier-frequency (CF) and intermediate-frequency (IF) pulse-width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF-PWM and precorrected CF-PWM, a fully digital transmitter with unit-delay autocalibration is implemented in 180 nm CMOS for high reconfiguration. The proposed architecture achieves wide CF range of 2 M–1 GHz, high power efficiency of 70%, and low error vector magnitude (EVM) of 3%, with spectrum purity of 20 dB optimized in comparison to the existing designs.

Implementation of prime-point DFTs with programable processors

Two existing DFT/FFT algorithms and a new prime-point Fast Fourier Transform algorithm are implemented with different serial and parallel processors. The evaluation results show that previous multiplication computational cost criterion is no longer applicable to the current parallel implementation. Total computational cost including add/subtract operation is one of the key factors affecting the speed and efficiency of implementation of parallel architecture.

A brief study on low-rate wireless personal network

Low-rate wireless personal network (LR-WPAN) is an emerging networking technique that was obtained more and more attention for its power efficient and low data rate applications. In this paper, we give a brief overview of WPAN and wireless senor network (WSN) protocols. Then, we focus on IEEE 802.15.4 which is the fundamental of many LR-WPAN protocols. Finally, we set up a simple experiment based on NS2 platform to evaluate the performance of it.

Polyhedral model based application source codes analysis for ASIP design

Application Specific Instructions-set Processors (ASIPs) are needed to handle the future demand of flexible and high performance computation in parallel real-time computing domain. Current ASIP design methodologies are mostly based on the accurate understanding of application source codes. Profilers can automatically analyse source codes and get interesting information from them to aid processor architecture design. Dynamic profilers add extra instructions to source codes and execute to generate basic block execution counts. This is often infeasible in the domain of parallel real-time computing, because of excessive execution time and the difficulty to define typical stimuli in the early architecture design phase. Static methods analyse source codes without executing them and are faster and more accurate than dynamic ones. The static analysis method proposed in this paper is based on polyhedral model. It identifies code segments that execute frequently, or named hot codes. It is usually a small part of the whole code base. This information is provided to the architecture designer as design guide. The hot codes may be implemented using custom function unit to optimize the efficiency of the whole system. A running example is used to illustrate the static method, and the results are compared to dynamic profilers. Same results are achieved by the two analysis methods.

A high-throughput and size-efficient NoC buffer design method

This paper presents a high-throughput and size efficient buffer design method for an application specific NoC. The method firstly configures on chip buffer according with the mapping position of IP and the routing path of communication pairs, then computes the minimum value of buffers size under NoC performance guarantee. Under the same buffer size, the experiments show that the method results in the 40% improvement of the throughput when compared the common input buffer design method.