Wenshen Li

600 V GaN vertical V-trench MOSFET with MBE regrown channel

GaN vertical power transistors have gained increasing interest in recent years due to the advantages over lateral transistors in high voltage/high current applications. To date, two major topologies have been studied most: gate-on-epi-surface (GoE) and gate-on-sidewall (GoS). The GoE devices include CAVET [1] and VDMOSFET-like transistors [2, 3]. The GoS devices include U-MOS or trench-MOSFETs with inversion channel [4, 5] or regrown AlGaN/GaN semi-polar channel [6], as well as depletion-mode MISFET [7]. The vertical MISFET is the simplest to fabricate, however, it does not have avalanche capabilities inherently besides being difficult to achieve sufficiently large Vth. It is easier for trench MOSFETs to achieve normally-off operation, high breakdown voltage (BV) and small footprint. However, it is challenging to achieve high mobility in the inversion channel. In contrast, CAVETs, VDMOS-like transistors and PolarMOS [3] utilize high mobility AlGaN/GaN channel to achieve low Ron, but the channel regrowth posts challenges in achieving low off-state leakage in un-gated regrowth interface. Recently, a novel design based on trench MOSFET is realized by MOCVD regrowth of a thin GaN interlayer [8]. Low Ron and high BV is achieved in the gated regrown channel. Similar to the other MOCVD regrown devices, the buried Mg-doped p-GaN needs to be re-activated by exposing the p-GaN surface during high temperature anneal. This leads to high thermal budget and poses limitations on device geometry. Furthermore, any incomplete activation of buried p-GaN leads to reduced BV. In this work, we design a V-shaped trench MOSFET with MBE regrown UID GaN channel. −600 V breakdown voltage with normally-off operation is demonstrated without the need for re-activation of the buried p-GaN. To our knowledge, this is the highest BV achieved in GaN vertical transistors with MBE regrown channel.

1.1-kV Vertical GaN p-n Diodes With p-GaN Regrown by Molecular Beam Epitaxy

High-voltage vertical regrown p-n junction diodes on bulk GaN substrates are reported in this letter with molecular-beam-epitaxy regrown p-GaN on metalorganic-chemical-vapor-deposition grown n-GaN drift region. The highest breakdown voltage is measured at 1135 V, and the differential on-resistance is 3.9 mOhm.cm2 at room temperature. The forward I–V show a turn-ON voltage near 3.9 V and an ideality factor of 2.5. Electroluminescence measurement of regrown p-n junctions shows ~30 times reduced emission intensity compared with as-grown p-n junctions, indicating presence of excessive non-radiative recombination centers introduced by the regrowth process. Temperature dependent reverse I–V measurements suggest that variable range hopping inside the depleted regrown p-GaN layer is likely the mechanism of the reverse leakage. This is the first high-voltage vertical regrown p-n junction ever reported in the GaN system.

Activation of buried p-GaN in MOCVD-regrown vertical structures

Thermal activation of buried p-type GaN is investigated in metal-organic chemical vapor deposition-regrown vertical structures, where the buried p-GaN is re-passivated by hydrogen during regrowth. The activation is performed by exposing the buried p-GaN through etched sidewalls and characterized by reverse breakdown measurements on vertical diodes. The effect of the n-type doping level on the activation has been observed. After 725 °C/30 min annealing in a dry air environment, the buried p-GaN with a regrown unintentionally-doped (UID) capping layer is sufficiently activated due to significant Mg-incorporation in the UID layer, allowing for hydrogen up-diffusion. With an additional regrown n+-GaN capping layer (i.e., in n+/i/p-n diodes), only lateral diffusion of H out of the exposed mesa sidewall is permitted. A critical lateral dimension between 10 and 20 μm is found for the n+/i/p-n diodes, under which the buried p-GaN is sufficiently activated. The diodes with activated buried p-GaN achieved up to 1200 V breakdown voltage, indicating that over 28% of the Mg dopants is activated. The study demonstrates the effectiveness of sidewall p-GaN activation in achieving high breakdown voltage pertinent to GaN vertical power devices, while providing guidelines on the required device geometry.Thermal activation of buried p-type GaN is investigated in metal-organic chemical vapor deposition-regrown vertical structures, where the buried p-GaN is re-passivated by hydrogen during regrowth. The activation is performed by exposing the buried p-GaN through etched sidewalls and characterized by reverse breakdown measurements on vertical diodes. The effect of the n-type doping level on the activation has been observed. After 725 °C/30 min annealing in a dry air environment, the buried p-GaN with a regrown unintentionally-doped (UID) capping layer is sufficiently activated due to significant Mg-incorporation in the UID layer, allowing for hydrogen up-diffusion. With an additional regrown n+-GaN capping layer (i.e., in n+/i/p-n diodes), only lateral diffusion of H out of the exposed mesa sidewall is permitted. A critical lateral dimension between 10 and 20 μm is found for the n+/i/p-n diodes, under which the buried p-GaN is sufficiently activated. The diodes with activated buried p-GaN achieved up to 120...

Breakdown mechanism in 1 kA/cm2 and 960 V E-mode β-Ga2O3 vertical transistors

A high current density of 1 kA/cm2 is experimentally realized in enhancement-mode Ga2O3 vertical power metal-insulator field-effect transistors with fin-shaped channels. Comparative analysis shows that the more than doubled current density over the prior art arises from a larger transistor channel width; on the other hand, a wider channel also leads to a more severe drain-induced barrier lowering therefore premature transistor breakdown at zero gate-source bias. The observation of a higher current density in a wider channel confirms that charge trapping in the gate dielectric limits the effective field-effect mobility in these transistor channels, which is about 2× smaller than the electron mobility in the Ga2O3 drift layer. The tradeoff between output-current density and breakdown voltage also depends on the trap density. With minimal trap states, the output current density should remain high while breakdown voltage increases with decreasing fin-channel width.

Vertical fin Ga 2 O 3 power field-effect transistors with on/off ratio >10 9

Recently, Ga<inf>2</inf>O<inf>3</inf> has become an attractive material for both power electronic and optoelectronic device applications since large-size electronic-grade Ga<inf>2</inf>O<inf>3</inf> substrates can be readily produced by melt-grown methods. Furthermore, high quality epitaxy and n-type doping schemes have been demonstrated [1, 2]. Due to its ultra-wide band gap (∼4.5–4.9 eV), Ga<inf>2</inf>O<inf>3</inf> is estimated to have a critical breakdown field >6 MV/cm, comparing favorably with ∼3 MV/cm in SiC and ∼4 MV/cm in GaN. This allows devices capable of handling large switching voltages. Devices such as lateral channel MOSFETs, MESFETs [3], MISFETs [4], nano-membrane FETs [5] and lateral FinFETs [6], vertical Schottky Barrier Diodes (SBDs) [7, 8], and deep-UV solar-blind photodetectors [9] have all been demonstrated using Ga<inf>2</inf>O<inf>3</inf>. Here, we report the first Ga<inf>2</inf>O<inf>3</inf> vertical power transistors with a breakdown voltage (BV) of 185 V.

GaN vertical nanowire and fin power MISFETs

GaN vertical power devices have many advantage over lateral device in device scaling, reliability and thermal management, etc. Traditional power transistors employ p-type pockets to achieve E-mode, RESURF and avalanche capabilities. However, this topology in GaN vertical power transistors has been challenging to implement [1] due to the difficulty to achieve selective area doping without compromising breakdown: p-type pockets in n-type regions or vice versa. The GaN UMOS-FETs or trench MOSFETs can be realized using epitaxial p-layers, however, suffer from low channel mobility in the inversion channel [2, 3]. Using n-type GaN only, depletion mode vertical MISFETs can be achieved with attractive current densities and breakdown voltages [4]. To get normally-off operation, Fin or nanowire (NW) pillars are necessary geometries. Compared with Fins, GaN nanowires have added advantages including superior electrostatic control and possibility for low-cost growth on foreign substrates [5, 6]. In this work, we report the first experimental demonstration of NW-MISFETs on bulk GaN substrates and compare them with Fin-MISFETs with the state-of-the-art performance fabricated on the same sample. The benefit of better electrostatic gate control in nanowire MISFETs are highlighted.