Wenzhe Zhao

Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory

Multi-level per cell (MLC) technique significantly improves storage density, but also poses new challenge to data integrity in NAND flash memory. Therefore, low-density parity-check (LDPC) code and soft-decision memory sensing have become indispensable in future NAND flash-based solid state drive design. However, these more powerful technologies inevitably increase the memory read latency and hence degrade the decoding throughput. Motivated by intra-cell unbalanced bit error probability and data dependency in MLC NAND flash memory, this paper proposes two techniques, i.e. intra-cell data placement interleaving and intra-cell data dependency aware min-sum decoding, to effectively improve the throughput of LDPC decoding. Experimental results show that, the proposed techniques used in an integrated way can improve the LDPC decoding throughput by up to 85% when the MLC NAND flash chip is heavily cycled, compared with conventional design practice.

Reducing latency overhead caused by using LDPC codes in NAND flash memory

Semiconductor technology scaling makes NAND flash memory subject to continuous raw storage reliability degradation, leading to the demand for more and more powerful error correction codes. This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as low-density parity-check (LDPC) codes become very natural alternative options. However, fine-grained soft-decision memory sensing must be used in order to fully leverage the strong error correction capability of LDPC codes, which results in significant data access latency overhead. This article presents a simple design technique that can reduce such latency overhead. The key is to cohesively exploit the NAND flash memory wear-out dynamics and impact of LDPC code structure on decoding performance. Based upon detailed memory device modeling and ASIC design, we carried out simulations to demonstrate the potential effectiveness of this design method and evaluate the involved trade-offs.

Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device

A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and the soft-decision memory sensing become indispensable in the next-generation flash-based solid-state storage devices. However, the use of LDPC codes inevitably increases memory read latency and, hence, degrades speed performance. Motivated by the observation of intracell unbalanced bit error probability and data dependence in the MLC NAND flash memory, this paper proposes two techniques, i.e., intracell data placement interleaving and intracell data dependence aware LDPC decoding, to efficiently improve the LDPC decoding throughput and energy efficiency for the MLC NAND flash-based storage in a mobile device. Experimental results show that, by exploiting the intracell bit-error characteristics, the proposed techniques together can improve the LDPC decoding throughput by up to 84.6% and reduce the energy consumption by up to 33.2% while only incurring less than 0.2% silicon area overhead.

A high performance and low cost video processing SoC for digital HDTV systems

This paper proposes a video processing SoC for Flat Panel Displays and describes the employed video processing algorithms. Three key techniques integrated in the proposed chip are introduced, including spatio-temporal adaptive TV decoder, square-nonlinear interpolation scaler and efficient memory controller. The overall video processing architecture is fabricated at 0.18um CMOS technology node, and the IC is extensively evaluated in a prototype HDTV Set. The proposed SoC chip can well supports both SDTV and HDTV signals, while providing high quality images.

Scheduling Algorithms for Handling Updates in Shingled Magnetic Recording

Shingled recording has recently emerged as one promising candidate to sustain the historical growth of magnetic recording storage areal density. However, since the convenient update-in-place feature is no longer available in shingled recording, many sectors must be read and written back in order to update one sector. This leads to a significant update-induced latency overhead and makes conventional hard disk drive scheduling algorithms perform poorly. This paper concerns with the development of appropriate scheduling algorithms for shingled recording based hard disk drives. We first present a simple partial-update scheduling algorithm that can naturally embrace the update latency issue and achieves significant gains over conventional scheduling algorithms. We enhance this algorithm by incorporating a shortest update first policy, which can further reduce the update response time on an average by 70%. Finally, motivated by abundant workload spatial and temporal locality, we develop a spatio-temporal band coalescing scheme that can achieve an additional reduction of update response time of up to 96.8%.

VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder

In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.