Werner Bux

Local-Area Subnetworks: A Performance Comparison

This paper provides a comparative evaluation of the performance of ring and bus systems constituting subnetworks of local-area networks. Performance is measured in terms of the delaythroughput characteristics. Systems investigated include token-controlled and slotted rings as well as random-access buses (CSMA with collision detection) and ordered-access buses. The investigation is based on analytic models which describe the various topologies and access mechanisms to a sufficient level of detail. The paper includes a comprehensive discussion of how the performance of the different networks is affected by system parameters like transmission rate, cable length, packet lengths, and control overhead.

Analysis of tuning of FDDI media access control protocol

The fiber distributed data interface (FDDI) provides a 100 Mb/s communication system to interconnect computer and peripheral equipment using fiber optics as the transmission medium in a ring configuration. The performance of the FDDI media-access control (MAC) protocol, a timed-token protocol, is analyzed. The FDDI MAC priority mechanism supports two classes of traffic: synchronous and asynchronous. The focus is on the relationship between the FDDI MAC parameter settings, the ring configuration, and the performance of the asynchronous priority levels. A procedure to calculate estimates for the throughput of each asynchronous priority level over a range of frame-arrival rates is developed. Performance results are presented to demonstrate characteristics of the FDDI priority mechanism. A procedure is described that can be used to tune the FDDI parameters so that given performance objectives for the various priority levels are achieved. >

Architecture and Design of a Reliable Token-Ring Network

Architecture, performance, transmission system, and wiring strategy of a token-ring local area network implemented at the IBM Zurich Research Laboratory are described. In the design of the system, particular emphasis was placed on high reliability, availability, and serviceability. To ensure robustness of the token-access protocol, we employ the concept of a monitor function which is responsible for fast recovery from access-related errors. Our protocol supports asynchronous transmission of data frames concurrently with full-duplex synchronous channels, e.g., for voice services or other applications requiring guaranteed delay. The delay-throughput performance of the token ring is shown to depend very little on data rate and distance. The transmission system of the ring is fully bit synchronous and allows insertion/removal of stations in/from the ring at any time. A mixed ring/star wiring strategy is used which provides the means for both fault detection and isolation, and system reconfiguration, and allows wiring of a building systematically.

Technologies and building blocks for fast packet forwarding

We provide a review of the state of the art and the future of packet processing and switching. The industrys response to the need for wire-speed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special programmable network processors. We discuss the prerequisites of processing tens to hundreds of millions of packets per second and indicate ways to achieve scalability through parallel packet processing. Tomorrows switch fabrics, which will provide node-internal connectivity between the input and output ports of a router or switch, will have to sustain terabit-per-second throughput. After reviewing fundamental switching concepts, we discuss architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance.

An Approximate Method for the Performance Analysis of Buffer Insertion Rings

A new analytic approach for the performance evaluation of buffer insertion rings is proposed which overcomes the basic limitations of former analyses. Key to our analysis is that the global performance model of a buffer insertion ring is decomposed into submodels in such a way that the basic interdependence of interarrival and transmission times of the frames transmitted is taken into account. The analysis itself is relatively straightforward and yields simple and explicit results for the mean delays of the frames. For special traffic patterns, the analysis is exact, for the general case, it is approximate but its accuracy turns out to be high, as comparison with simulation results shows.

Token-ring local-area networks and their performance

The major technical concepts underlying token-ring technology are examined, and performance issues arising in the design of such local-area networks (LANs) are detailed. Following a survey of analytical queuing models to describe the basic token-ring operation, three topics are discussed in detail: (1) the IEEE 802.5 token ring and its performance; (2) the ANSI fiber distributed data interface (FDDI) token ring and its performance; and (3) architecture and performance issues arising in the interconnection of token-ring networks with regard to the various components of a multiring architecture demonstrating which congestion-control problems can arise in such a network and how they can be overcome. The author concludes with a number of open questions concerning the understanding of the quantitative behavior of token-ring-based LANs. >

Balanced HDLC Procedures: A Performance Analysis

The prime objective of the present paper is to analyze the performance of HDLC Balanced Class of Procedures, i.e., to quantitatively study the interaction among a multiplicity of parameters which are procedure specific, characterize the properties of the transmission medium, and identify the operational characteristics and requirements. The approach taken is to consider two kinds of operation: a saturated case characterized by maximum throughput as the most suitable measure of performance, and a nonsaturated situation for which waiting and transfer times are the appropriate measures. The analysis is performed by means of both simulation and analytic techniques. Within the simulation model, the information transfer phase of the HDLC procedure was implemented in full detail. The key idea of the analytic approach is to use a so-called virtual transmission time, a quantity comprising both the real constant transmission time of a message and the duration of recovery actions in case of transmission errors. It allows the performance measures to be represented by explicit and easily-computable expressions. The results provide a fundamental insight into how the most relevant parameters interact and determine performance.

Performance issues in local-area networks

This paper discusses several important performance problems in the design of local-area networks. The questions discussed relate to various aspects of architecture, design, and implementation: (1) the delaythroughput characteristics of the medium access protocols, (2) the performance of local-area networks on which a file server provides file storage and retrieval services to intelligent workstations, and (3) timing problems in local-area network adapters. Since the paper does not primarily addressth e performance analyst, it is descriptive in nature; analytic details are omitted in favor of a more intuitive explanation of the relevant effects.

DQMA and CRMA: new access schemes for Gbit/s LANs and MANs

Distributed-queue multiple-access (DQMA) and cyclic-reservation multiple-access (CRMA) access schemes for gigabit-per-second local and metropolitan area networks are described. These schemes are based on a slotted unidirectional bus structure, with both folded and dual-bus configurations. Like the distributed-queue dual-bus (DQDB) scheme, both the DQMA and the CRMA access schemes achieve full throughput independent of network speed and distance. They have two significant advantages over DQDB. They provide throughput fairness even at high speeds and large distances, where DQDB exhibits dramatic unfairness, and, by allowing reservation of multiple consecutive slots, they make segment labeling unnecessary and facilitate packet reassembly significantly.<<ETX>>

Performance of greedy garbage collection in flash-based solid-state drives

In flash-based solid-state drives (SSD) and log-structured file systems, new data is written out-of-place, which over time exhausts the available free space. New free space is created by the garbage-collection process, which reclaims the space occupied by invalidated data. The write amplification, incurred because of the additional write operations performed by the garbage-collection mechanism is a critical factor that negatively affects the lifetime and endurance of SSDs. We develop two complementary theoretical models of the SSD operation for uniformly-distributed random small user writes: a Markov chain model, which is useful to explore the performance characteristics of small and medium-sized systems, and a second model that captures the behavior of large systems. The combination of both models allows us to comprehensively characterize the system operation and behavior. Results of theoretical and practical importance are analytically derived and confirmed by means of simulation. Our results demonstrate that (i) as the system occupancy increases, the write amplification increases; (ii) as the number of blocks increases, the write amplification decreases and approaches a lower bound; and (iii) as the number of pages contained in a block increases, the write amplification increases and approaches an upper bound. They also show that, for large systems, the number of free pages reclaimed by the greedy garbage-collection mechanism after each block recycling takes one of two successive values, which provides a quasi-deterministic performance guarantee.