Werner Gillijns

Standard cell design in N7: EUV vs. immersion

While waiting for EUV lithography to become ready for adoption, we need to create designs compatible with both EUV single exposures as well as with 193i multiple splits strategy for technology nodes 7nm and below needed to keep the scaling trend intact. However, the standard approach of designing standard cells in two-dimensional directions is no more valid owing to insufficient resolution of 193-i scanner. Therefore, we propose a standard cell design methodology, which exploits purely one-dimensional interconnect.

Impact of a SADP flow on the design and process for N10/N7 Metal layers

This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes a couple of solutions. For the N10 design, we opted for a line staggering approach in which each line-end ends on a contact. We highlight the challenges to obtain a reasonable process window, both in simulation as on based on exposures on wafer. The main challenges come from a very complex keep mask, consisting of complicated 2D structures which are very challenging for 193i litho. Therefore, we propose a solution in which we perform a traditional LELE process on top of a mandrel layer. Towards N7 we show that a line staggering approach starts to break down and design needs to allow better process window for lithography by having metal lines ending in an aligned fashion. has many challenges and we propose to switch to a line cut approach. A more lithography friendly approach is needed for design where the lines end at aligned points so that the process window can be enhanced.

Metal oxide EUV photoresist performance for N7 relevant patterns and processes

Inpria continues to leverage novel metal oxide materials to produce high resolution photoresists for EUV lithography with high optical density and etch resistance. Our resists have previously demonstrated 13nm line/space patterns at 35 mJ/cm2, with extendibility to 10nm half-pitch.1 We have continued to improve photospeed and in this work we provide an update on imaging performance. Since practical patterns for EUV layers will be more complicated than line/space patterns, we also expand on our previous work by demonstrating 2D resist performance using N7 (7nm node) contact and block mask patterns on full field scanners. A resist model has been created and using this model comparisons are made between a metal oxide resist and CAR platforms. Based on this physical model, the impact of shot noise is examined in relation to realistic 2D features. Preliminary data on the effect on OPC of using a non-chemically amplified resist are also presented.

Patterning process exploration of metal 1 layer in 7nm node with 3D patterning flow simulations

In 7mn node (N7), the logic design requires the critical poly pitch (CPP) of 42-45nm and metal 1 (M1) pitch of 28- 32nm. Such high pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with triple litho-etch (LE3) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent 3D profile and topology. We use this tool to study the patterning process variations of N7 M1 layer including the overlay control, the critical dimension uniformity (CDU) budget and the lithographic process window (PW). The resulting 3D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field and identify hot spots for dielectric reliability. As an example application, we will report extractions of maximum electric field at M1 tipto- tip which is one of the most critical patterning locations and we will demonstrate the potential of this approach for investigating the impact of process variations on dielectric reliability. We will also present simulations of an alternative M1 patterning flow, with a single exposure block using extreme ultraviolet lithography (EUVL) and analyze its advantages compared to the LE3 block approach.

Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform

This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.

Reticle enhancement techniques toward iN7 metal2

The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent metal layers1. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5. Regarding the metal 2 layer, imec is evaluating two integration approaches: EUV single print and SAQP+EUV Block. Extensive work is reported on both approaches2,3. The work detailed in this paper will deal about the computational work done prior to tape-out for the EUV direct print option. We will discuss the EUV source mask optimization for an ASML NXE:3300 EUV scanner. Afterwards we will shortly touch upon OPC compact modeling and more extensively on OPC itself. Based on the current design rules and MRC, printability checks indicate that only limited process windows are obtained. We propose ways to improve the printability through MRC and design. Applying those changes can potentially lead to a sufficient process window.

Compact 2D OPC modeling of a metal oxide EUV resist for a 7nm node BEOL layer

Inpria has developed a directly patternable metal oxide hard-mask as a high-resolution photoresist for EUV lithography1. In this contribution, we describe a Tachyon 2D OPC full-chip model for an Inpria resist as applied to an N7 BEOL block mask application.

Modeling the topography of uneven substrates post spin-coating

The semiconductor industry has followed Moores law for many decades and is currently preparing for high-volume manufacturing of the 7 nm technology node. To further scale down to the 5 nm technology node and below, research centers are constantly testing novel patterning and integration approaches. To enable a number of these new integration approaches, there is a growing need for a well-understood and well-controlled tone reversal technology. Tone reversal consists in inverting the tonality of all structures present on a wafer, e.g., turning a hole pattern into a pillar pattern. Examples of applications that advantageously integrate such tone reversal technology are multiple litho-etch block patterning, the fully self-aligned block concept, and the direct metal etch approach. A critical step in the tone reversal process is to achieve a good wafer planarization, i.e., limited wafer topography. This can be done by chemical mechanical polishing after filling the patterned features that need to be tone inverted. However, a more promising approach is to reduce the topography by using a planarizing spin-coating process to fill the patterns. Material vendors and research groups have done tremendous efforts to understand and improve the quality (uniformity, planarity, etch resistance, etc.) of spin-coating processes. When a spin-coating process is used to fill a given patterned structure, it is known that the degree of planarization is impacted by a set of parameters such as pattern width and density. However, it is not clear yet what the exact functional dependence is. In this work, the authors first present an experimental study of the planarization behavior of spin-coated materials as a function of pattern width, depth, and density. The authors observed a strong dependency of the width and the density of the patterns on the wafer topography post spin-coating, while the depth, within the boundaries of this study, showed no significant impact. The most striking result was the observation of the linear relationship between the pattern density difference between two areas and the relative height difference of those areas after spin-coating. Second, based on these experimental observations, the authors present a model that predicts the remaining wafer topography post spin-coating. The model calculates the topography for a given set of structures, using only one parameter as input. This parameter is a fixed number for a specific spin-coating process and is called the planarization length λ. The authors demonstrate that this model is capable of reproducing and predicting the experimentally measured height profiles on complex patterned structures for different spin-coating processes. These calculations can be done with commercially available electronic design automation software. Therefore, this model can become a powerful tool in mask design, both for applications based on tone reversal, and, in general, for patterning processes that make use of spin-coated materials.The semiconductor industry has followed Moores law for many decades and is currently preparing for high-volume manufacturing of the 7 nm technology node. To further scale down to the 5 nm technology node and below, research centers are constantly testing novel patterning and integration approaches. To enable a number of these new integration approaches, there is a growing need for a well-understood and well-controlled tone reversal technology. Tone reversal consists in inverting the tonality of all structures present on a wafer, e.g., turning a hole pattern into a pillar pattern. Examples of applications that advantageously integrate such tone reversal technology are multiple litho-etch block patterning, the fully self-aligned block concept, and the direct metal etch approach. A critical step in the tone reversal process is to achieve a good wafer planarization, i.e., limited wafer topography. This can be done by chemical mechanical polishing after filling the patterned features that need to be tone inve...

EUV pupil optimization for 32nm pitch logic structures

A pupil optimization was carried out for the M2 layer of the imec N7 (foundry N5 equivalent) logic design. This is exposed as a single print EUV layer. We focused on the printability of the toughest parts of the design: a dense line space grating of 32 nm pitch and a tip-tip grating of 32 nm pitch, tip-to-tip target CD of 25 nm. We found that the pupil optimization can improve both the line space and the tip-to-tip gratings energy latitude and depth of focus. The tip-to-tip target CD can be pushed further, enabling further design scaling.

Single exposure EUV of 32nm pitch logic structures: patterning performance on BF and DF masks

This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.