Will X. Y. Li

Real-Time Prediction of Neuronal Population Spiking Activity Using FPGA

A field-programmable gate array (FPGA)-based hardware architecture is proposed and utilized for prediction of neuronal population firing activity. The hardware system adopts the multi-input multi-output (MIMO) generalized Laguerre-Volterra model (GLVM) structure to describe the nonlinear dynamic neural process of mammalian brain and can switch between the two important functions: estimation of GLVM coefficients and prediction of neuronal population spiking activity (model outputs). The model coefficients are first estimated using the in-sample training data; then the output is predicted using the out-of-sample testing data and the field estimated coefficients. Test results show that compared with previous software implementation of the generalized Laguerre-Volterra algorithm running on an Intel Core i7-2620M CPU, the FPGA-based hardware system can achieve up to 2.66×103 speedup in doing model parameters estimation and 698.84 speedup in doing model output prediction. The proposed hardware platform will facilitate research on the highly nonlinear neural process of the mammal brain, and the cognitive neural prosthesis design.

Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform

The Burrows-Wheeler Transform (BWT) based methodology seems ideally suited for DNA sequence alignment due to its high speed and low space complexity. Despite being efficient in exact matching, the application of BWT in inexact matching still has problems due to the excessive backtracking process. This paper presents a hardware architecture for the BWT-based inexact sequence mapping algorithm using the Field Programmable Gate Array (FPGA). The proposed design can handle up to two errors, including mismatches and gaps. The original recursive algorithm implementation is dealt with using hierarchical tables, and is then parallelized to a large extension through a dual-base extension method. Extensive performance evaluations for the proposed architecture have been conducted using both Virtex 6 and Virtex 7 FPGAs. This design is considerably faster than a direct implementation. When compared with the popular software evaluation tool BWA, our architecture can achieve the same match quality tolerating up to two errors. In an execution speed comparison with the BWA aln process, our design outperforms a range of CPU platforms with multiple threads under the same configuration conditions.

High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity

A hardware-based computational platform is developed to model the generalized Laguerre–Volterra (GLV) multiple-input multiple-output (MIMO) system which is essential in identification of the time-varying neural dynamics underlying spike activities. Time cost for model parameters estimation is greatly reduced by a significant enhancement of 3.1

An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking

\,\times 10^{3}~{\rm x}

Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform

in data throughput of the Xilinx XC6VSX475T field programmable gate array (FPGA)-based system compared to a C model running on an Intel i7–860 Quad Core processor. The processing core consists of a first stage containing a vector convolution and MAC (multiply and accumulation) component; a second stage containing a prethreshold potential updating unit with an error approximation function component; and a third stage consisting of a gradient calculation unit. The hardware platform is scalable with the utilization of different number of processing units within each stage. It is also easily extendable into a multi-FPGA structure to further enhance the computational capability. A hardware IP library is proposed for versatile neural models and applications. The implementation of the self-reconfiguring platform and its applications to future research of neural dynamics are explored.

A dual mode FPGA design for the hippocampal prosthesis

Abstract Recent studies have verified the efficiency of stochastic state point process filter (SSPPF) in coefficients tracking in the modeling of the mammalian nervous system. In this study, a hardware architecture of SSPPF is both designed and implemented on a field-programmable gate array (FPGA). It provides a time-efficient method to investigate the nonlinear neural dynamics through coefficients tracking of a generalized Laguerre–Volterra model describing the spike train transformations of different brain sub-regions. The proposed architecture is able to process matrices and vectors with arbitrary sizes. It is designed to be scalable in parallel degree and to provide different customizable levels of parallelism, by exploring the intrinsic parallelism of the FPGA. Multiple architectures with different degrees of parallelism are explored. This design maintains numerical precision and the proposed parallel architectures for coefficients estimation are also much more power efficient.

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

Secure processors have become increasingly important for trustworthy computing as security breaches escalate. By providing hardware-level protection, a secure processor ensures a safe computing environment where confidential data and applications can be protected against both hardware and software attacks. In this paper, we present a single-chip secure processor model and demonstrate rapid prototyping of the secure processor on the OpenSPARC FPGA platform. OpenSPARC T1 is an industry-grade, open-source, FPGA-synthesizable general-purpose microprocessor originally developed by Sun Microsystems, now acquired by Oracle. It is a multi-core, multi-threaded 64-bit processor with open-source hardware, including the microprocessor core, as well as system software that can be freely modified by researchers. We modify the OpenSPARC T1 processor by adding security modules: an AES engine, a TRNG and a memory integrity tree. These enhancements enable security features like memory encryption and memory integrity verification. By prototyping this single-chip secure processor on the FPGA platform, we find that the OpenSPARC T1 FPGA platform has many advantages for secure processor research. Our prototyping demonstrates that additional modules can be added quickly and easily and they add little resource overhead to the base OpenSPARC processor.

Laguerre-Volterra model and architecture for MIMO system identification and output prediction.

One important step towards the cognitive neural prosthesis design is to achieve real-time prediction of neuronal firing pattern. An FPGA-based hardware computational platform is designed to guarantee this hard real-time signal processing requirement. The proposed platform can work in dual modes: generalized Laguerre-Volterra model parameters estimation and output prediction, and can switch between these two important system functions. Compared with the traditional software-based platform implemented in C, the hardware platform achieves better efficiency in doing the biocomputations by up to thousandfold speedup in this process.

A reconfigurable architecture for real-time prediction of neural activity

Neural coding is an essential process for neuroprosthetic design, in which adaptive filters have been widely utilized. In a practical application, it is needed to switch between different filters, which could be based on continuous observations or point process, when the neuron models, conditions, or system requirements have changed. As candidates of coding chip for neural prostheses, low-power general purpose processors are not computationally efficient especially for large scale neural population coding. Application specific integrated circuits (ASICs) do not have flexibility to switch between different adaptive filters while the cost for design and fabrication is formidable. In this research work, we explore an application specific instruction set processor (ASIP) for adaptive filters in neural decoding activity. The proposed architecture focuses on efficient computation for the most time-consuming matrix/vector operations among commonly used adaptive filters, being able to provide both flexibility and throughput. Evaluation and implementation results are provided to demonstrate that the proposed ASIP design is area-efficient while being competitive to commercial CPUs in computational performance.

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities

A generalized mathematical model is proposed for behaviors prediction of biological causal systems with multiple inputs and multiple outputs (MIMO). The system properties are represented by a set of model parameters, which can be derived with random input stimuli probing it. The system calculates predicted outputs based on the estimated parameters and its novel inputs. An efficient hardware architecture is established for this mathematical model and its circuitry has been implemented using the field-programmable gate arrays (FPGAs). This architecture is scalable and its functionality has been validated by using experimental data gathered from real-world measurement.