Willard Stuart Briggs

A 17 /spl times/ 69 bit multiply and add unit with redundant binary feedback and single cycle latency

The authors describe a numeric processor with a kernel that is a tree of redundant binary adders and effects either a 17 /spl times/ 69-b multiply-and-add or a 19 /spl times/ 69-b multiply with exact redundant binary output and single cycle latency. Feedback paths selectively allow a high-order or low-order part of the adder tree output to be fed back in redundant binary form to the multiplicand and/or addend inputs to the adder tree. The authors describe algorithms iteratively using this adder tree kernel for IEEE double extended multiplication, division, and square root; conversions between 18-digit BCD integers and 64-b binary integers; and transcendental function evaluation. The multiplier design described was implemented in the Cyrix 83D87 numeric coprocessor (typically 33 MHz). Results for this coprocessor as compared with competitive x87 units are included.<<ETX>>