William Chou

Mask contribution to intra-field wafer overlay

Shrinking wafer overlay budgets raise the importance of careful characterization and control of the contributing components, a trend accelerated by multi-patterning immersion lithography [1]. Traditionally, the mask contribution to wafer overlay has been estimated from measurement of a relatively small number of standard targets. There are a number of studies on test masks and standard targets of the impact of mask registration on wafer overlay [2],[3]. In this paper, we show the value of a more comprehensive characterization of mask registration on a product mask, across a wide range of spatial frequencies and patterns. The mask measurements will be used to obtain an accurate model to predict mask contribution to wafer overlay and correct for it.

Hotspot analysis and empirical correction through mask and wafer technology harmonization

Design weak points that have narrow process window and limits wafer yield, or hotspots, continue to be a major issue in semiconductor photolithography. Resolution enhancement techniques (RET) such as advanced optical proximity correction (OPC) techniques and source mask optimization (SMO) are employed to mitigate these issues. During yield ramp for a given technology node, full-chip lithography simulation, pattern-matching and machine learning are adopted to detect and remedy the weak points from the original design [1], [2]. This is typically an iterative process by which these points are identified in short-loop lithography testing. Design retarget and/or OPC modifications are made to enhance process window until the yield goal is met. This is a high cost and time consuming process that results in a slow yield ramp for existing production nodes and increased time to market (TTM) for new node introduction. Local hotspot correction through mask and wafer harmonization is a method to enhance wafer yield with low cost and short cycle time compared to the iterative method. In this paper, a fast and low cost approach to hotspot correction is introduced. Hotspots were detected on wafer after OPC and characterized by using advanced mask characterization and optimization (AMCO) techniques. Lithographic simulations and AIMS measurement were used to verify the hotspot correction method. Finally, the validity of this new approach was evaluated by process window analysis and circuit probe yield test at wafer.

Process window discovery from mask inspection for hotspot analysis and verification

A new technology transforms mask inspection images through focus into 3D lithography images in resist. This enables early detection and ranking of hotspots, and distinguishes mask-induced and process-induced hotspots. The results can be used in several ways including: 1) feed back to OPC teams to improve process window; 2) feed forward to the litho team for scanner adjustment; and, 3) feed forward to wafer inspection in the form of care areas to reduce time to result for wafer-based process window discovery.

The CD control improvement by using CDSEM 2D measurement of complex OPC patterns

As the process node becomes more advanced, the accuracy and precision in OPC pattern CD are required in mask manufacturing. CD SEM is an essential tool to confirm the mask quality such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in some cases of arbitrary enclosed patterns or aggressive OPC patterns, for instance, line with tiny jogs and curvilinear SRAF, CD variation depending on region of interest (ROI) is a very serious problem in mask CD control, even it decreases the wafer yield. For overcoming this situation, the 2-dimensional (2D) method by Holon is adopted. In this paper, we summarize the comparisons of error budget between conventional (1D) and 2D data using CD SEM and the CD performance between mask and wafer by complex OPC patterns including ILT features.

UDOF direct improvement by modulating mask absorber thickness

As the process generation migrate to advanced and smaller dimension or pitch, the mask and resist 3D effects will impact the lithography focus common window severely because of both individual depth-of-focus (iDOF) range decrease and center mismatch. Furthermore, some chemical or thermal factors, such as PEB (Post Exposure Bake) also worsen the usable depth-of-focus (uDOF) performance. So the mismatch of thru-pitch iDOF center should be considered as a lithography process integration issue, and more complicated to partition the 3D effects induced by optical or chemical factors. In order to reduce the impact of 3D effects induced by both optical and chemical issues, and improve iDOF center mismatch, we would like to propose a mask absorber thickness offset approach, which is directly to compensate the iDOF center bias by adjusting mask absorber thickness, for iso, semi-iso or dense characteristics in line, space or via patterns to enlarge common process window, i.e uDOF, which intends to provide similar application as Flexwave[1] (ASML trademark). By the way, since mask absorber thickness offset approach is similar to focus tuning or change on wafer lithography process, it could be acted as the process tuning method of photoresist (PR) profile optimization locally, PR scum improvement in specific patterns or to modulate etching bias to meet process integration request. For mass production consideration, and available material, current att-PSM blank, quartz, MoSi with chrome layer as hard-mask in reticle process, will be implemented in this experiment, i.e. chrome will be kept remaining above partial thru-pitch patterns, and act as the absorber thickness bias in different patterns. And then, from the best focus offset of thru-pitch patterns, the iDOF center shifts could be directly corrected and to enlarge uDOF by increasing the overlap of iDOF. Finally, some negative tone development (NTD) result in line patterns will be demonstrated as well.

In die mask overlay control for 14nm double-patterning lithography

According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy. Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget. In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.

The study of phase angle effects to wafer process window using 193-nm EAPSM in a 300-mm wafer manufacturing environment

As the semiconductor-process technology advances towards the 90nm-node, more and more wafer-fabs start to use 193nm EAPSM (Embedded Attenuated Phase-Shift Mask) technology as the main lithography strategy for the most critical-layers. Because the 193nm EAPSM is a relative new technology in the semiconductor industry, it is important for us to understand the key-mask-specifications in a 193nm EAPSM and their impact to the wafer process windows. In this paper, we studied the effects of phase-angle and transmission to the wafer process window of a 193nm-EAPSM in a 300mm wafer-manufacturing environment. We first fabricated a special multi-phase EAPSM by a combination of extra Quartz-etch and Mosi-removal. We then used a high NA 193nm scanner (ASML-ALTA1100) and high contrast resist to perform the wafer-level printing study. To fully understand the impact of phase-angle and transmission to wafer process windows, we also used AIMS (Aerial-Image Measurement System) and Prolith simulation software to study the lithographic performances of various phase-angle and transmission combinations. By combining the wafer-level resist imaging printing results, AIMS studies and Prolith-2 lithography simulations, we proposed the practical phase-angle and transmission specifications for the 90nm-node wafer process.

AIMS-fab SPEC for defect repair and better repair profile

For current mask defect repair, depending only on an inspection metrology tool (KLA-SLF77) to judge wafer printability is not enough. Many mask makers and users are turning to simulation-based photomask qualification to reduce unnecessary repairs and confirm defect repair. Using programmed defects of known size, phase, and location, we fabricated binary and Att PSM test masks to perform the repair. Utilizing Carl Zeiss’ Aerial Image Measurement System (AIMS-fab), we compared reticle simulation results to actual wafer image prints and then established a criteria SPEC as the core judgment rule. The investigation shows for binary L/S layout, the better repair profile received a wider ED-window for the wafer process. For Att PSM contact layout, the proper depth of quartz etching for smaller miss-contact was also demonstrated.

Characterization of repairs to KrF 300mm wafer printability for 0.13μm design rule with attenuated phase-shifting mask

For sub-0.13um lithography, attenuated phase shifting mask (AttPSM) with optical proximity correction (OPC) is reported as one of the potential methods to achieve manufacturable process by using 248nm exposure wavelength. Unfortunately, the low-k1 imaging process in 130nm lithography imposes much more stringent requirements on defect repair, especially on AttPSM reticle. Therefore, the imperfect repairs will have a significant impact on wafer process window due to quartz damage and phase distortion caused by Ga+ ion stain removal and added carbon material, respectively. In this paper, we have prepared AttPSM test masks having programmed defects with various opaque defects. Each defect area was inspected with KLA-Tencors SLF27 inspection system to acquire defect coordinates and image, simulated with AIMS to assess the intensity and transmission loss induced by repair process. All of masks were made by DuPont Photomasks Taiwan (DPT) by using the Jbx9000MV2 E-beam writer and dry Chrome etch process. All lithographic experiments were performed on 300mm wafer using high NA ASML AT750S scanner and high contrast CAR resist. In this study, we have focused on the impact of quartz damage and phase error on wafer process window by comparing the wafer CD and pattern profile through focus. In order to establish a efficient way to perform effective judgement on repair defect between mask shop and wafer fab, both AIMS and wafer results will be compared and correlated.