William H. Kautz

Nonrandom binary superimposed codes

A binary superimposed code consists of a set of code words whose digit-by-digit Boolean sums (1 + 1 = 1) enjoy a prescribed level of distinguishability. These codes find their main application in the representation of document attributes within an information retrieval system, but might also be used as a basis for channel assignments to relieve congestion in crowded communications bands. In this paper some basic properties of nonrandom codes of this family are presented, and formulas and bounds relating the principal code parameters are derived. Finally, there are described several such code families based upon (1) q -nary conventional error-correcting codes, (2) combinatorial arrangements, such as block designs and Latin squares, (3) a graphical construction, and (4) the parity-check matrices of standard binary error-correcting codes.

Fibonacci codes for synchronization control

A new family of codes is described for representing serial binary data, subject to constraints on the maximum separation between successive changes in value (0 \rightarrow 1, 1 \rightarrow , or both), or between successive like digits ( 0 s, 1 s, or both). These codes have application to the recording or transmission of digital data without an accompanying clock. In such cases, the clock must be regenerated during reading (receiving, decoding), and its accuracy controlled directly from the data itself. The codes developed for this type of synchronization are shown to be optimal, and to require a very small amount of redundancy. Their encoders and decoders are not unreasonably complex, and they can be easily extended to include simple error detection or correction for almost the same additional cost as is required for arbitrary data.

Testing for Faults in Wiring Networks

An algorithm is derived for multiprobe testing for shorts, opens, and wiring errors in any multiterminal wiring network, such as a printed circuit board, wiring harness, multiconductor cable, or backplane wiring board. For behavioral testing the minimum number of tests required, always achievable, is equal to p - 1 + [log2q], where p is the number of terminals in the largest interconnected cluster in the network, and q is the total number of clusters, including isolated terminals. For structural testing the number of tests required is less, and can be as small as [log2q] + 1 depending upon the assumptions made regarding the types of faults that can occur.

Cellular Interconnection Arrays

Abstract—A class of networks is described that has the capability of permuting in an arbitrary manner a set of n digital input lines onto a set of n digital output lines. The circuitry of the networks is arranged in cellular form, i. e., in a two-dimensional iterative pattern with mainly local intercell connections, where the basic cell behaves as a reversing switch with a single memory flip-flop. Various network forms are described, differing in the number of cells needed, in the shape of the array, and in the length and regularity of intercell connections. Also discussed are some ways of setting up the array to achieve a desired permutation.

Fault Testing and Diagnosis in Combinational Digital Circuits

Abstract—he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail. By testing and diagnosis we mean the following: 1) detection of a fault, 2) location of a fault, and 3) location of a fault within the confines of a prescribed package or module. It is shown that minimal test schedules can be readily derived–using procedures already worked out for solving certain problems in pattern recognition and switching theory–under the assumption that the selection of the test inputs in the schedule is independent of the response of the circuit under test. When this assumption is not made, it is shown that much shorter test schedules are sometimes possible, and procedures are offered for obtaining good ones. Finally, the general status of diagnostics for digital circuits is reviewed and evaluated, and specific problems remaining to be solved are described.

The Realization of Symmetric Switching Functions with Linear-Input Logical Elements

The problem of synthesizing switching networks out of linear-input (threshold) elements is studied for the class of symmetric switching functions. Tight bounds are derived for the number of elements required in a minimal realization, and a method of synthesis is presented which yields economical networks. Minimal networks result for all symmetric functions of no more than about twelve variables, and for several other cases. In particular, it is shown how the parity function of any number n of variables can be realized with about log2(n) elements.

The Necessity of Closed Circuit Loops in Minimal Combinational Circuits

A cellular-logic approach is used to generate a family of multiple-output combinational switching circuits containing closed loops ( of the type that normally generate sequential behavior) and composed of simple gates. These networks contain fewer gates than any loop-free realizations. Some members of the family are oscillatory, while others are stable with multiple stable states, but the outputs remain quiescent in both cases. This result appears to have repercussions on some of the well-known optimality results of switching theory.

Cellular arrays for the solution of graph problems

A cellular array is a two-dimensional, checkerboard type interconnection of identical modules (or cells), where each cell contains a few bits of memory and a small amount of combinational logic, and communicates mainly with its immediate neighbors in the array. The chief computational advantage offered by cellular arrays is the improvement in speed achieved by virtue of the possibilities for parallel processing. In this paper it is shown that cellular arrays are inherently well suited for the solution of many graph problems. For example, the adjacency matrix of a graph is easily mapped onto an array; each matrix element is stored in one cell of the array, and typical row and column operations are readily implemented by simple cell logic. A major challenge in the effective use of cellular arrays for the solution of graph problems is the determination of algorithms that exploit the possibilities for parallelism, especially for problems whose solutions appear to be inherently serial. In particular, several parallelized algorithms are presented for the solution of certain spanning tree, distance, and path problems, with direct applications to wire routing, PERT chart analysis, and the analysis of many types of networks. These algorithms exhibit a computation time that in many cases grows at a rate not exceeding log2 n, where n is the number of nodes in the graph. Straightforward cellular implementations of the well-known serial algorithms for these problems require about n steps, and noncellular implementations require from n2 to n3 steps.

A Cellular Threshold Array

The purpose of this paper is to describe the design of an all-digital cellular threshold array that is well adapted to realization by large-scale integrated semiconductor technology. A set of these arrays may be interconnected to realize arbitrary combinational or sequential logic, or may be stacked to form a multilevel adaptive pattern classification machine.

An Augmented Content-Addressed Memory Array for Implementation With Large-Scale Integration

A design is presented for an augmented content-addressed memory (ACAM) that can realize arbitrary combinational and sequential logic as well as a repertoire of simultaneously executed but varying word-organized operations. The ACAM array is offered as a useful and efficient module that is highly compatible with large-scale-integrated (LSI) device technology, and which can be used to construct a central processor, certain related peripheral subsystems, and possibly for general digital applications as well. An ACAM is a rectangular cellular array in which all cells are identical and each cell contains both storage and combinational logic. Data words are stored along rows of the array, and all operations are parallel (single-clock). Horizontal operations include shifting, column entry and readout, and several types of tests--equality, size (~_ and >), binary inclusion, zero, and overflow. In the vertical direction, one may perform vertical shifting (whole words at a time), entry, readout, logical and Boolean addition, full binary addition, complementation, and masking. Within certain limitations, word operations are selected independently for separate words in the array, and most operations may be masked on certain digits of all words or on certain words in all digit positions or both. The basic cell has a complexity of about 40 NOR-gates. In addition to its general-purpose parallel-processing capability, the ACAM array may also be utilized for many special purposes, such as a pushdown memory, a queue (buffer) memory, a bank of index registers, a scratchpad memory, a sorting memory (which keeps in order all words inserted in it), a conventionally addressed memory, and a list memory (based on any of a variety of data structures). By virtue of its combinational capability, the array may be employed as a data encoder or decoder, a permutation array (like a crossbar switch), a correlator for binary signal sequences, or a microprogram control matrix.