William K. C. Lam

Delay Fault Coverage and Performance Tradeoffs

The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, all known analysis and synthesis techniques for 100% path delay fault testability are infeasible on most circuits. In this paper, we show that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it; hence these delay faults need not be considered in delay fault testing. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed can be selected such that 100% robust delay fault coverage is achieved.

Delay fault coverage, test set size, and performance trade-offs

The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, this implies very large test sets for most circuits. Not surprisingly, all known analysis and synthesis techniques for 100% path delay fault testability are computationally infeasible on large circuits. We prove that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it. These are termed robust dependent delay faults and need not be considered in delay fault testing. Necessary and sufficient conditions under which a set of path delay faults is robust dependent are proved; this yields more accurate and increased delay fault coverage estimates than previously used. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed (clock period) can be selected such that 100% robust delay fault coverage is achieved. This leads to a quantitative tradeoff between the testing effort (measured by the size of the test set) for a circuit and the verifiability of its performance. Finally, under a bounded delay model, we show that the test set size can be reduced while maintaining the delay fault coverage for the specified circuit speed. Examples and experimental results are given to show the effect of these three techniques on the amount of delay fault testing necessary to guarantee correct operation. >

Valid clocking in wavepipelined circuits

An analysis of valid clock rates in wavepipelined circuits using a technique called timed Boolean functions is presented. It is shown that the valid intervals for the clock period can be disconnected. Thus, it is insufficient to known only the minimum valid clock period in guaranteeing proper operation of pipelined circuits. Analytic expressions for the valid clock intervals in terms of both topological delay and two-vector longest and shortest delays are provided. Also uncertainties arising from manufacturing are taken into account. Some potential difficulties in computing the exact valid clock intervals are illustrated by demonstrating discontinuity and nonmonotonicity of the harmonic number H( tau ) (the number of valid simultaneous data waves allowed) as a function of the clock period tau .<<ETX>>

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions

We propose a general circuit delay model that unifies all previous delay models, e.g. floating, viability, and transition delays, and models introduced in this paper, e.g. delays by sequences of vectors and minimum delays. Then, we formulate the computation of the exact circuit delays, under both bounded and unbounded gate delay models, as a mixed Boolean linear programming using a new formulation technique, called Timed Boolean Function. Next, we compute the exact delays of combinational circuits for transition delay and delay by sequences of vectors. We show that delays by sequences of vectors and floating (or viability) delays are invariant under both bounded and unbounded gate delay models. Finally, we address the effect of gate delay lower bounds on delays of circuits. We demonstrate the effectiveness of the method by giving exact delay results for all ISCAS benchmark circuits (except C6188).

Valid clock frequencies and their computation in wavepipelined circuits

It is known that wavepipelined circuits offer high performance, because their maximum clock frequencies are limited only by the path delay differences of the circuits, as opposed to the longest path delays. For proper operation, precision in clock frequency is essential. Using a new representation, Timed Boolean Functions, we derive analytical expressions for valid clocking intervals in terms of topological, 2-vector, and single vector delays, both the longest and the shortest. These intervals take into account both circuit functionality and timing characteristics, thus eliminating the pessimism caused by long and short false paths, and include effects of circuit parameters such as delay variations, clock skews, and setup and hold times of flip flops. In addition, we show that these intervals subsume Cottens lower bound on valid clock period. Further, we study the problem of computing all enact valid clocking intervals and its computational complexity by demonstrating discontinuity and nonmonotonicity of the harmonic number H(/spl tau/) (the number of valid simultaneous data waves allowed) as a function of the clock period /spl tau/. Finally, we propose algorithms to compute the exact valid intervals for a given set of harmonic numbers and demonstrate performance enhancement of balanced circuits from ISCAS benchmarks with gate delay variations.

Exact Minimum Cycle Times for Finite State Machines

In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though these methods deal with false paths, they ignore the sequential and periodic nature of minimum cycle times, and hencemay give pessimistic results. In this paper, we first prove conditions under which combinational delays are correct upper bounds on minimum cycle times. Then, we present a sequential approach to compute the minimum cycle times of finite state machines, taking into account the effects of gate delay variations, reachable state space, initial states, unrealizable transitions, multiple cycle false paths, and periodicity of the present state vector sequences. We formulate and solve the problem exactly using Timed Boolean Functions, and give an efficient algorithm to solve for upper bounds of minimum cycle times. The exact formulation with Timed Boolean Functions provides a framework for further improvements on existing algorithms to compute the minimum cycle times. We implemented the algorithm and obtained the tightest bounds known on ISCAS benchmarks. From the experiments, we found that for about 20%of the circuits (not all shown in section 8), combinational delays, e.g. floating, viability, and transition delays, give pessimistic upper bounds for cycle times by as much as 25%.

Alternating RQ Timed Automata

Two major difficulties in verification with timed automata are state explosion and dependence of complexity on time constants, even with restricted timing constraints. Based on the observation that a vast majority of timed automata have a very regular timing structure, We propose a class of timed automata, alternating RQ timed automata, andprove that they have simple pathpropertieswhich, even with arbitrary timing constraints, yield efficient verification algorithms. In addition, the complexity of the algorithms is independent of the time constants. Next, we give graphical necessary and sufficient conditions for timed automata to be RQ alternating. Finally, we discuss verification algorithms of alternating RQ L-automata (L-processes).

Timed Boolean Functions

In timing research, the entire temporal behaviors of circuits are studied; thus, a representation technique capturing temporal properties should be devised. In this chapter, we propose Timed Boolean Functions (TBF’s) as a representation formalism for timing analysis and study its properties in formulating circuits with both logical and timing functionalities. Finally, we derive decision diagrams for TBF’s.

On relationship between ITE and BDD

Properties of the if-then-else directed-acyclic graph (ITE) and its relation to the binary decision diagram (BDD) are investigated. It is shown that, for any given variable ordering, there are fewer exponential ITEs than BDDs, and that, for any function f, the size of its canonical ITE is bounded by 4* the size of its corresponding canonical BDD, i.e. //ITE(f)//<4*//BDD(f)//. However, for most MCNC benchmarks, //ITE// approximately=2*//BDD//. It is also shown that the controlling functions of ITEs are maximal with respect to addition, multiplication, and complementation. A graphical relationship between ITEs and BDDs is demonstrated, and algorithms for obtaining canonical ITEs from canonical BDDs, and vice versa, are proposed.<<ETX>>

Criteria for the Simple Path Property in Timed Automata

Timed automata have been studied in the past and have been found to have a complexity dependent on the relative scale of the time constants involved in the timing constraints imposed, even if the timing constraints are restricted to the form x<k where x is a clock variable and k is a constant. We have previously shown that this complexity dependence on the time constants can be eliminated if the timed automaton has the simple path property (state A is reachable from state B if and only if it is reachable along a path with no cycles), and gave a set of conditions on the placement of clock queries and resets which imply this simple path property. These automata were called alternating RQ timed automata. We gave a technique for using this properly to iteratively constrain an untimed automaton to rule out simple paths which cannot meet their timing constraints. The simple path property means that only simple paths need be constrained. In this paper, we give conditions for a timed automaton with arbitrary constraint equations to have the simple path property. As far as we know all practical examples in the literature meet these criteria. For example, this includes all automata with constraints of the form for each state s, a trace must remain in s for a time t where \(t_{s_{min} } < t < t_{s_{max} }\). We are currently working on an efficient implementation for timed automata where arbitrary linear inequalities among the clock values are allowed. Using linear programming, we iteratively detect simple paths which are not traversable and construct untimed automata which disallow these paths. The present paper serves to extend this approach to a wide class of applications. In addition, we define extended RQ timed automata which include all the examples in the literature and are easily tested for this property.