William Martin Snelgrove

SIMD processor arrays for image and video processing: A review

SIMD processor arrays are becoming popular for their fast parallel executions of low- to medium-complexity image and video processing algorithms, and most stages of the compression standards. In many existing techniques, visual data processing algorithms and compression standards possess a high degree of parallelism. In particular, the processing of a certain pixel/block does not generally require data from a distant pixel/block, and the instructions for processing these pixels/blocks are usually identical. Thus, these algorithms map naturally onto the architecture of the SIMD processor arrays. In this paper, the architectures of the recently SIMD processor arrays will be reviewed together with algorithms demonstrating their superior features. Due to the length of the paper, only processor arrays implemented at the chip-level are discussed, especially those whose logic circuits are merged/embedded in the SRAM or DRAM memory process. While some processor arrays are designed by embedding the memory modules onto the existing processors, a significant number of processor arrays are realized by integrating logic circuits onto existing RAM to save the inherently large memory bandwidth, and thus achieving a performance in the order of Tera instructions per second.

Fast motion estimation using feature extraction and XOR operations

Motion estimation is a temporal image compression technique where an n X n block of pixels in the current frame of a video sequence is represented by a motion vector with respect to the best matched block in a search area of the previous frame, and the DCT coefficients of the estimated error terms. In this paper, a fast technique for motion estimation is proposed and later mapped onto the SIMD structure of the computational*RAM (C*RAM). C*RAM is a conventional computer DRAM with built-in logic circuitry at the sense-amplifier to take advantage of the high on-chip memory bandwidth and massively parallel SIMD operations. The proposed technique, first, attempts to reduce the n-bit grayscale frames into 1-bit binary frames using morphological filters, and to search for motions of the extracted features on the binary frames. While the reduction procedure requires a small percentage of computation using the full grayscale, the search procedure is performed by simple XOR logic operations and 1-b distortion accumulations on the entire search area. The second part of the paper presents the mapping of the proposed technique onto the C*RAM architecture.

Computational RAM implementation of MPEG-2 for real-time encoding

In this paper, a computational random access memory (C*RAM) implementation of MPEG-2 video compression standard is presented. This implementation has the advantage of processing image/video data in parallel and directly in the frame buffers. Therefore, savings in execution time and I/O bandwidth due to massively parallel on-chip computation and reduction in the data transfer among chips is achieved. As a result, MPEG-2 video encoding can be realized in real-time on a programmable 64 Mb DRAM-based C*RAM.