William R. Dieter

A user-level checkpointing library for POSIX threads programs

Several user-level checkpointing libraries that checkpoint Unix processes have been developed. However they do not support multithreaded programs. This paper describes a user-level checkpointing library to checkpoint multithreaded programs that use the POSIX threads library provided by Solaris 2. Experiments with programs from the SPLASH-2 benchmark suite showed a 3% to 10% increase in execution time with checkpointing enabled, plus an additional overhead for saving the programs state. The checkpointing library described here is available at http://www.dcs.uky.edu//sup /spl sim//chkpt/.

Compiler and runtime support for predictive control of power and cooling

The low cost of clusters built using commodity components has made it possible for many more users to purchase their own supercomputer. However, even modest-sized clusters make significant demands on the power and cooling infrastructure. Minimizing impact of problems after they are detected is not as effective as avoiding problems altogether. This paper is about achieving the best system performance by predicting and avoiding power and cooling problems. Although measuring power and thermal properties of a code is not trivial, the primary issue is making predictions sufficiently in advance so that they can be used to drive predictive, rather than just reactive control at runtime. This paper presents new compiler analysis supporting interprocedural power prediction and a variety of other compiler and runtime technologies making feed-forward control feasible. The techniques apply to most computer systems, but some properties specific to clusters and parallel supercomputing are used where appropriate.

Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy

Some processors designed for consumer applications, such as graphics processing units (CPUs) and the CELL processor, promise outstanding floating-point performance for scientific applications at commodity prices. However, IEEE single precision is the most precise floating-point data type these processors directly support in hardware. Pairs of native floating-point numbers can be used to represent a base result and a residual term to increase accuracy, but the resulting order of magnitude slowdown dramatically reduces the price/performance advantage of these systems. By adding a few simple microarchitectural features, acceptable accuracy can be obtained with relatively little performance penalty. To reduce the cost of native-pair arithmetic, a residual register is used to hold information that would normally have been discarded after each floating-point computation. The residual register dramatically simplifies the code, providing both lower latency and better instruction-level parallelism.

Sparse flat neighborhood networks (SFNNs): scalable guaranteed pairwise bandwidth & unit latency

Network performance for a particular application is determined by the latency and bisection bandwidth that are achieved for the set of specific communication patterns used by that application. The number of nodes with which each node might potentially communicate grows linearly as nodes are added, thus, network cost for large systems either becomes a large fraction of machine cost or performance suffers. However, performance-critical communication patterns commonly occurring in real parallel programs rarely require that each node directly communicate with every other node. The number of node pairs actually communicating generally grows far slower than the expected O(N/sup 2/). Thus, a carefully designed network for a massively parallel system can use relatively narrow switches while still providing single-switch latency and guaranteed pairwise bandwidth for performance-critical communications. This paper introduces sparse flat neighborhood networks (SFNNs), a variant of flat neighborhood networks (FNNs) which are engineered from first principles to efficiently meet these detailed pairwise communication performance criteria.

Scanning for extinct astrobiological residues and current habitats (SEARCH)

SEARCH is a new method to seek evidence of extinct life and potential habitats. SEARCH combines innovative spectroscopic integrated sensing and processing with a hyperspace data-analysis algorithm. Using UV, visible, and near-IR spectroscopic integrated sensing and processing, SEARCH is designed to explore and quantitatively assess a local region on the surface of a planet or moon as a potential habitat for life, past or present. In the course of collecting geological data, SEARCH spectrometry can investigate planetary processes of relevance to past habitability, including the role of water. In addition to its own investigations, SEARCH can be used at a distance to guide a rover to areas of interest for application of other analysis tools. Several prototype implementations of SEARCH have been developed and initial experimental results are presented along with a design for a full-scale version of SEARCH for Mars exploration.

Computer Aided Engineering of Cluster Computers

There are many scientific and engineering applications that require the resources of a dedicated supercomputer: drug design, weather prediction, simulating vehicle crashes, fluid dynamics simulations of aircraft or even consumer products. Cluster supercomputers can leverage commodity parts with standard interfaces that allow them to be used interchangeably to build supercomputers customized for these and other applications. However, the best design for one application is not necessarily the best design for other applications. Supercomputer design is challenging, but this problem is harder due to the huge range of possible configurations, volatile component availability and pricing, and constraints on available power, cooling, and floor space. Cluster design rules (CDR) is a computer-aided engineering tool that uses resource constraints and application performance models to identify the few best designs among the trillions of designs that could be constructed using parts from a given database. It uses a branch-and-bound strategy based on cluster design principles that can eliminate many inferior designs from the search without evaluating them. For the millions of designs that remain, CDR measures fitness by one of several user-specified application performance models. New application performance models can be added by means of a programming interface. This paper details the concepts and mechanisms inside CDR and shows how it facilitates model-based engineering of custom clusters.