William Ralph Hunter

1 µm MOSFET VLSI technology: Part V—A single-level polysilicon technology using electron-beam lithography

An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 µm, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etchback after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed.

Effects of component imperfections on ellipsometer calibration

The accuracy of determination of film properties from ellipsometer measurements is determined by the accuracy with which ψ and Δ can be measured. This paper examines the effects of off-diagonal elements in the Jones matrices on calibration measurements in P -A, P -C -A, and P -S -A configurations. Based on these results, specific calibration procedures for determining instrument constants are given that will minimize the effects of off-diagonal elements. In particular, the method of McCrackin et al. for determining the polarizer–prism offset is found to be influenced by off-diagonal elements, and a simpler method based on extinction readings is presented. The advantages of using a sample with ρ˜=±j during P -S -A calibration measurements and a subsequent P -C -S -A check are pointed out. Polarizer–prism beam deviation in combination with photomultiplier sensitivity variations has been found to be a source of error. However, a specific procedure for determining the relative phase retardation δ′ of the compensator in the P -C -A configuration is described, which eliminates beam-deviation effects.

Effects of detector nonlinearity on calibration and data reduction of rotating-analyzer ellipsometers

Small nonlinearity (~2%) of the light-flux detection system is shown to have appreciable effects on the accuracy of calibration and data analysis in rotating-analyzer ellipsometers. Procedures for detecting and correcting these effects are presented.

One-micrometer electron-beam lithography FET technology

An n-channel silicon gate technology, using electron-beam lithography with minimum dimensions of 1 µm, has been implemented for FET logic applications. The six mask process employs semi-recessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques and reactive ion etching (RIE). A description of the process is given, with particular emphasis or topographical considerations. Implementation of a field etchback after source and drain implant to eliminate a low thick-oxide parasitic device threshold is also discussed.