William Robert Lee

Designing systerns-on--chip using cores

Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increasingly relying on reuse of Intellectual property (IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. That is the goal, in theory. In practice, assembling on SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discusses the main challenges in SoC designs using IP blocks and elaborates on the methodology and tools being put in place at IBM for addressing the problem. It explains IBMs SoC architecture and gives algorithmic details on the high-level tools being developed for SoC design.

Formal verification of an IBM coreconnect processor local bus arbiter care

This paper describes the model checking effort for an arbiter core for the IBM CoreConnect Architecture. We present our verification methodology and describe how it was influenced by the architecture. We also present and analyze the bugs found and discuss the difficulties associated with verifying complex on-chip buses, highlighting the need for better tools and methodologies for their specification and verification.