William S. Graham

High-speed signal propagation on lossy transmission lines

This paper addresses some of the problems encountered in propagating high-speed signals on lossy transmission lines encountered in high-performance computers. A technique is described for including frequency-dependent losses, such as skin effect and dielectric dispersion, in transmission line analyses. The disjoint group of available tools is brought together, and their relevance to the propagation of high-speed pulses in digital circuit applications is explained. Guidelines are given for different interconnection technologies to indicate where the onset of severe dispersion takes place. Experimental structures have been built and tested, and this paper reports on their electrical performance and demonstrates the agreement between measured data and waveforms derived from analysis. The paper addresses the problems found on lossy lines, such as reflections, rise-time slowdown, increased delay, attenuation, and crosstalk, and suggests methods for controlling these effects in order to maintain distortion-free propagation of high-speed signals.

A 10.5-in.-diagonal SXGA active-matrix display

A 157-dot-per-inch, 262K-color, 10.5-in.- diagonal, 1280 × 1024 (SXGA) display has been fabricated using a six-mask process with Cu or Al-alloy thin-film gates. The combination of high resolution and gray-scale accuracy has been shown to render color images and text with paperlike legibility. The low-resistivity gate metallization and trilayer-type TFTs with a channel length of 6-8 µm were fabricated with a six-mask process which is extendible to larger, higher-resolution displays. A combination of double-sided driving and active line repair was used so that open gate lines or data lines did not result in visible line defects. A flexible drive-electronics system was developed to address the display and characterize its performance under different drive conditions.

A six-mask TFT-LCD process using copper-gate metallurgy

— A novel reduced mask process is used to fabricate high-resolution high-aperture-ratio 10.5-in. SXGA (1280 × 1024) displays. The process uses copper gate-metallurgy with redundancy, without the need for extra processing steps. The resulting displays have 150-dpi color resolution, an aperture ratio of over 35%, and excellent image quality, making them the first high-resolution displays that are suitable for notebook applications.

Fabrication and performance studies of multilayer polymer/metal interconnect structures for packaging applications

Multilayer copper/polyimide interconnect structures were fabricated using a reactive-ion-etching-based lift-off technique. Conductor cross-sectional area control, planarity, and a gap-free structure were made possible by the use of a novel siloxane-polyimide. The resultant structure consisted of two signal wiring layers between two ground planes with a nominal impedance of 40 Omega . Although redundant metallization processes were found to repair open lines, they resulted in an increase of the number of processing steps and could result in an increase of defects. Stud chain structures were found to survive cooling to 77 K with very little change in their characteristics, while heating of the copper interconnections to 350 degrees C in a reducing environment reduced their resistance by 3%.<<ETX>>

Factors affecting the interconnection resistance and yield in multilayer polyimide/copper structures

The use of a lift-off technique to fabricate a high-density structure consisting of multiple layers of metal/polyimide thin-film structures on a silicon substrate is described. To achieve better performance and high yield, the process design, the processing parameters, the thickness of the Cr/Cu/Cr metallurgy, and the use of suitable polyimide dielectrics, were evaluated. The plasma processing conditions, the types of passivation metals on Cu, and the use of a siloxane-polyimide as the gap-fill/etch-stop material were all shown to play a critical role in affecting the interconnection resistance and yield of the multilayer thin-film structures. By optimizing these parameters the feasibility of fabricating high-density thin-film wiring layers with good yield is demonstrated. >

Patterning of CMOS device structures for 40-80nm pitches and beyond

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.

Factors affecting the interconnection resistance and yield in the fabrication of multilayer polyimide/metal thin film structures

The use of a lift-off technique to fabricate a high-density structure consisting of multiple layers of metal/polyimide thin film structure on a silicon substrate is described. To achieve better performance and high yield, the authors evaluated the process design, the processing parameters, and the thickness of the Cr/Cu/Cr metallurgy, along with the use of suitable polyimide dielectrics. The plasma processing conditions, the types of passivation metals on Cu, and the use of a siloxane-polyimide as the gap-fill etch-stop material were all shown to play a very critical role in affecting the interconnection resistance and yield of the multilayer thin film structures. By optimizing these parameters the feasibility of fabricating high-density thin film wiring layers with good yield is demonstrated.<<ETX>>

High-performance thick copper inductors in an RF technology

With the emergence of wired and wireless communication technologies, on-chip inductors find applications in a variety of high performance radio frequency (RF) circuits. In this work, we present two approaches for high-performance copper inductors in an RF technology. In the first approach (Type I), we lower ohmic losses to realize a high Q-factor. This is achieved by using, for the first time in a manufacturable technology, 4 μm thick copper spirals along with a 4 μm thick copper underpass on high-resistivity substrates (75 Ω-cm). The underpass is connected to the spirals with a 4 μm tall copper via, which lowers spiral to underpass capacitance. For further lowering the capacitive losses, an additional 6.1 μm thick interlayer dielectric separates the underpass from the substrate. In the second approach (Type II), we utilize a novel one-mask CMOS-compatible micromachining scheme to eliminate substrate losses. This is achieved by completely removing the silicon substrate from directly below the inductors. For a 1.1nH inductor, peak-Q shows an impressive two-fold improvement from 26.6 at 3.8 GHz for Type I inductor to 52.8 at 8.2 GHz for Type II inductor after silicon micromachining. The resonant frequency increases from 18 GHz to 27 GHz after substrate micromachining.