William W. Macy

Efficient implementation of sorting on multi-core SIMD CPU architecture

Sorting a list of input numbers is one of the most fundamental problems in the field of computer science in general and high-throughput database applications in particular. Although literature abounds with various flavors of sorting algorithms, different architectures call for customized implementations to achieve faster sorting times. This paper presents an efficient implementation and detailed analysis of MergeSort on current CPU architectures. Our SIMD implementation with 128-bit SSE is 3.3X faster than the scalar version. In addition, our algorithm performs an efficient multiway merge, and is not constrained by the memory bandwidth. Our multi-threaded, SIMD implementation sorts 64 million floating point numbers in less than0.5 seconds on a commodity 4-core Intel processor. This measured performance compares favorably with all previously published results. Additionally, the paper demonstrates performance scalability of the proposed sorting algorithm with respect to certain salient architectural features of modern chip multiprocessor (CMP) architectures, including SIMD width and core-count. Based on our analytical models of various architectural configurations, we see excellent scalability of our implementation with SIMD width scaling up to 16X wider than current SSE width of 128-bits, and CMP core-count scaling well beyond 32 cores. Cycle-accurate simulation of Intels upcoming x86 many-core Larrabee architecture confirms scalability of our proposed algorithm.

Robust frame-dependent video watermarking

In this paper, we describe some of the problems associated with watermarking key management, with particular attention to the case of video. We also describe a possible solution to the problem, which is that of image-dependent watermarking, and briefly discuss some of the possible advantages to be gained from adopting such an approach. The paper also presents a simple, efficient means of robustly extracting bits from a video sequence. The algorithm has applications to secure, oblivious video watermark detection.

Quality evaluation of watermarked video

Watermarks not specifically designed to be visible should be imperceptible to maintain image or video quality. Watermark characteristics that affect visibility include watermark magnitude, the visual masking model used to determine relative magnitude values, watermark frequency content, and the degree of temporal variation of the watermark between frames. Video characteristics that affect the visibility of a watermark include subject and camera motion, color, resolution, texture, and patterns. We have investigated the effects of these characteristics on watermark visibility for MPEG-1, MPEG-2, and both uncompressed and compressed high-definition video. The average watermark strength that can be added to a video is determined by increasing the average watermark magnitude through the sequence in order to observe the point at which the watermark becomes perceptible. The first artifact to become visible depends on video and watermark characteristics.

Characterizing multimedia kernels on general-purpose processors

Media applications have been driving microprocessor development for more than a decade. Future multimedia applications will have much higher computational requirements. Indeed, tomorrows PC experiences will be even richer in audio-visual effects, easier to use, and, more importantly, computing will merge with communications. Such application characteristics will differ from current application characteristics and thus, a new detailed analysis of such kernels is required. This paper proposes a selection of key kernels we believe will be prominent across applications running on future processors. An extensive study of these applications on current general-purpose processor architectures makes it possible to determine future media and communication characteristics and to identify bottlenecks that are not well addressed in current designs.

Real-time detection of video watermark on Intel architecture

This work discusses implementation issues of real-time video/image/signal processing applications on personal computers. We give a list of performance optimization guidelines and demonstrate some examples by optimizing our video watermark detection scheme. In many applications, watermarking technology must have (1) the ability to be implemented at low cost, (2) robustness against common image processing operations, and (3) resilience against purely malicious attacks. Many works, including ours, have demonstrated watermark robustness and invisibility. This work demonstrates that, after some performance optimizations, we can decode a 704 X 480 MPEG-2 video and detect the watermarks, both in software, and display the decoded video frames in real-time on an Intel PentiumR III 500 MHz system. Currently, there is only 10.5% overhead of the watermark detection over video decoding. The cost of our optimized implementation is 43% lower than that of the unoptimized version. The optimization techniques demonstrated in this work can be applied to other watermarking schemes and other video/image/signal processing applications.

Computational analysis and system implications of video watermarking applications

The aim of this paper is to analyze the computational requirements of video watermarking algorithms running on PC-based systems and to study their implication for the design of general-purpose processors and systems. Selected watermarking algorithms are analyzed from a computational point of view. Application examples are executed on current general-purpose processor architecture to understand the computational requirements and to detect potential bottlenecks. In addition to this workload analysis, the potential exploitation of data level parallelism through the use of SIMD instructions available on current architectures is evaluated. Thread level parallelism schemes is also studied in current watermarking in order to understand the potential benefit of simultaneous multithreading processors and symmetric multiprocessor systems for such applications. Even if the study of the different watermarking algorithms is crucial to understand the requirements of a system, it is not sufficient. Indeed, watermarking schemes are very often only one kernel in a complete application and the interaction between the watermarking kernel and the rest of the application can highly influence the computational and memory bandwidth requirements of the system. Therefore the example of watermarking detection in a video decoder is used to understand the additional system implications due to the merging of video decoding and watermarking algorithms.