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Dive into the research topics where William Wheeler is active.

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Featured researches published by William Wheeler.


electronic imaging | 1997

Architecture of a flexible real-time video encoder/decoder: the DECchip 21230

Matthew J. Adiletta; Debra Bernstein; Joel S. Emer; Samuel Ho; William Wheeler

Compression of video data is a highly compute-intensive activity consisting of both regular vector-style computations and general algorithmic computations. Furthermore, the conventional compression algorithms allow the encoder some degrees of freedom in the encode process, where picture quality and degree of compression can be traded off for amount of computation. These characteristics have led to a variety of approaches to video encoding. At one extreme, real-time compression can be achieved through the use of high performance vector and general purpose co- processors to generate high compression ratios and high quality. At the other end of the spectrum, compression can be performed in real-time quite easily by doing minimal analysis of the picture to enhance quality or improve compression. The DECchip 21230 strikes a compromise between these two extremes by supporting the regular vector-style computations on an inexpensive co-processor chip, but does most of the general algorithmic computation on the host CPU. This partitioning leads to a number of scheduling and buffering challenges that are addressed by a novel decomposition of the encoding process.


Archive | 2003

Thread signaling in multi-threaded network processor

Gilbert Wolrich; Debra Bernstein; Donald F. Hooper; Matthew J. Adiletta; William Wheeler


Archive | 2003

Microengine for parallel processor architecture

Debra Bernstein; Donald F. Hooper; Matthew J. Adiletta; Gilbert Wolrich; William Wheeler


Archive | 1999

Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode

Matthew J. Adiletta; Gilbert Wolrich; William Wheeler


Archive | 1999

SRAM controller for parallel processor architecture including address and command queue and arbiter

Matthew J. Adiletta; William Wheeler; James Redfield; Daniel Cutter; Gilbert Wolrich


Archive | 1999

Arbitrating command requests in a parallel multi-threaded processing system

Gilbert Wolrich; Debra Bernstein; Matthew J. Adiletta; William Wheeler


Archive | 2001

Method and apparatus for low overhead multithreaded communication in a parallel processing environment

Matthew J. Adiletta; Debra Bernstein; Gilbert Wolrich; William Wheeler


Archive | 2002

SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues

Matthew J. Adiletta; William Wheeler; James Redfield; Daniel Cutter; Gilbert Wolrich


Archive | 2001

READ LOCK MISS CONTROL AND QUEUE MANAGEMENT

Gilbert Wolrich; Daniel Cutter; William Wheeler; Matthew J. Adiletta; Debra Bernstein


Archive | 2000

Memory shared between processing threads

Gilbert Wolrich; Matthew J. Adiletta; William Wheeler; Daniel Cutter; Debra Bernstein

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