Wim J.C. Melis

Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementation of one such user support system, namely an intention estimation information appliance system, on a Bayesian Network as well as Hierarchical Temporal Memory. The latter is a new and quite promising soft computing platform modelling the human brain, though currently only available as a software model. A second part of the paper therefore focuses on a possible VLSI architecture for Hierarchical Temporal Memory. Since it models the human brain, communication as well as memory are of high importance for this VLSI architecture.

Image registration of real-time video data using the SONIC reconfigurable computer platform

This paper is concerned with the image registration problem as applied to video sequences that have been subjected to geometric distortions. This work involves the development of a computationally efficient algorithm to restore the video sequence using image registration techniques. An approach based on motion vectors is proposed and is found to be successful in restoring the video sequence for any affine transform based distortion. The algorithm is implemented in FPGA hardware targeted for a reconfigurable computing platform called SONIC It is shown that the algorithm can efficiently restore the video data in realtime.

A Study of the Different Uses of Colour Channels for Traffic Sign Recognition on Hierarchical Temporal Memory

When designing intelligence for a car many different tasks can be performed. Some of these tasks cannot easily be performed by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. In this paper, Hierarchical Temporal Memory (HTM) is used to implement one of these tasks, namely traffic sign recognition. In implementing this traffic sign recognition task, it is noticed that the use of colour is of particular importance, and that colour information should be treated in a particular way to optimise the recognition. However it is also noticed that there are still a significant number of differences between the modelling of the brain and how the brain actually deals with colour and object recognition.

Evaluation of Hierarchical Temporal Memory for a Real World Application

A large number of real world applications, such as user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Such intelligence is often implemented, by using probability based systems. This paper focuses on comparing the implementation of a cellular phone intention estimation example on a Bayesian Network and Hierarchical Temporal Memory. It is found that Hierarchical Temporal Memory is a system that requires little effort for designing the application, and with some extra effort, further optimised results can easily be obtained.

Autonomous Memory Block for reconfigurable computing

Current FPGAs include large blocks of memory that require separate address generation circuits. This not only uses logic resources surrounding the memory blocks, but also results in unnecessary routing congestions. This paper proposes the integration of the address generation circuit into the block memory to form an Autonomous Memory Block (AMB). Quantitative comparison between using AMB and conventional FPGA block memory architectures demonstrates that this approach is promising.

Increasing solar panel efficiency in a sustainable manner

Solar panel output is determined by a number of factors: obviously there is the type of panel that determines the conversion efficiency, but also the amount of light falling into the panel is of importance, among other conditions of operation. The output of a panel would e.g. drop when the amount of light falling onto it is reduced, or even when only a part of the panel is covered. Another reason for reduced output lies in the fact that the conversion efficiency drops by about 0.38 % per °C increase in panel temperature. Considering that a panel would be able to produce most of its output on a sunny day, the reduction in efficiency due to heating up is of significant importance. To achieve an optimised output, it is therefore important for the panel to remain clean, but also keep it as cool as possible. Therefore, this paper looks at a method of running water on top of a solar panel in order to clean it and cool it down. To reduce the energy consumption of moving the water from the bottom of the panel back to the top, it exploits the kinetic energy of the water that runs down the panel to pump the water back to the top. Measurements indicate that this approach leads to an average increase in output of about 12 %.

Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer

This paper is concerned with the image registration problem as applied to real-time video. It describes the development of a computationally efficient algorithm to restore broadcast quality video sequences using image registration techniques. A motion vector based approach is used and found to be successful in restoring the video sequence for any global perspective transform based distortion. The algorithm is implemented on a reconfigurable computing platform called UltraSONIC in a hardware/software codesign environment. It is shown that the algorithm can accurately restore video data in real-time.

Analogue auto-associative memory using a multi-valued memristive memory cell

Most brain-like computing systems build up from neural networks. While there are some essential problems with this approach, it is well-known that the brain functionally operates as an associative memory. Building associative memories using conventional CMOS technology has already been performed, but this approach suffers from a lack of scalability and information density. Additionally, for a long time, one of the differences between analogue and digital electronics was the fact that digital electronics allowed for easier data storage through a variety of different memory cell architectures. These memory designs make extensive use of transistors and generally trade area, performance and power. However, memristors can be used as high density, analogue, passive storage elements and this paper presents 2 memory cell designs that allow for such multi-valued storage. The noise resistance of these cells is tested and indicates a very good tolerance to external influences, while overall they provide for a very accurate storage of data with high information density. Following on from the description of the storage cells, the paper then continues to build them into an associative memory.

Reducing data storage requirements for machine learning algorithms using principle component analysis

While current computers have shown to be particular useful for arithmetic and logic implementations, their accuracy and efficiency for applications such as e.g. face, object and speech recognition, are not that impressive, especially when compared to what the human brain can do. Machine learning algorithms have been useful, especially for these type of applications, as they operate in a similar way to the human brain, by learning the data provided and storing it for future recognition. Until now, there has been a strong focus on developing the process of data storage and retrieval, merely neglecting the value of the provided information and the amount of data required to store. Hence, currently all information provided is stored, because it is difficult for the machine to decide which information needs to be stored. Consequently, large amounts of data are stored, which then affects the processing of the data. Thus, this paper investigates the opportunity to reduce data storage through the use of differentiation and combine it with an existing similarity detection algorithm. The differentiation isWhile current computers have shown to be particular useful for arithmetic and logic implementations, their accuracy and efficiency for applications such as e.g. face, object and speech recognition, are not that impressive, especially when compared to what the human brain can do. Machine learning algorithms have been useful, especially for these type of applications, as they operate in a similar way to the human brain, by learning the data provided and storing it for future recognition. Until now, there has been a strong focus on developing the process of data storage and retrieval, merely neglecting the value of the provided information and the amount of data required to store. Hence, currently all information provided is stored, because it is difficult for the machine to decide which information needs to be stored. Consequently, large amounts of data are stored, which then affects the processing of the data. Thus, this paper investigates the opportunity to reduce data storage through the use of differentiation and combine it with an existing similarity detection algorithm. The differentiation is achieved through the use of, Principal Component Analysis (PCA), which not only reduces the data storage requirements by about 80%, but also improves the overall detection accuracy around 50 to nearly 80%. achieved through the use of, Principal Component Analysis (PCA), which not only reduces the data storage requirements by about 80%, but also improves the overall detection accuracy around 50 to nearly 80%.

Hierarchical neural network model with intrinsic timing

In order to overcome some of the challenges that current, conventional computing faces, a large set of research is being performed into unconventional computing platforms, most often inspired by discoveries in neuroscience. This tends to result in Artificial Neural Networks, which are commonly an oversimplified version of their biological equivalent, where various aspects are being ignored, e.g. the aspect of time. This tends to prevent these networks from handling temporal sequences directly in the time domain. Hence, this research studies how the intrinsic timing of a neuron cell can be used to design a hierarchical neural network with feedback. The network is based on a simple Leaky Integrate and Fire RC-model for each neuron where the intrinsic timing is determined by the capacitor discharge. The results show that the model is able to differentiate between temporally different stimuli. Moreover, feedback allows the model to put lower level cells in a predictive state. Finally, the hierarchical model allows for higher-level cells to remain stable for a longer period and therefore allow for a better combination of sequential information at lower levels.