Wim Vanderbauwhede

An Analytical Performance Model for the Spidergon NoC

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discrete- event simulator.

A survey of patent users: an analysis of tasks, behavior, search functionality and system requirements

With a growing interest in Patent Information Retrieval, there is a need to better understand the context associated with patent users, their tasks, needs and expectations of patent search systems and applications. Patent search is known to be a complex, difficult and challenging activity, usually requiring expert Patent Information Specialists to spend a substantial amount of time sourcing (or not) documents relevant to their particular task. Information Retrieval provides a whole array of possible techniques and tools which could be applied to ease the burden of such retrieval tasks, and also make searching patents more accessible to non-Patent Information Specialists. In this paper, we report the findings from a survey of patent users conducted to ascertain information about patent users and their search requirements with respect to Information Retrieval systems and applications.

High-Performance Computing Using FPGAs

High-Performance Computing using FPGA covers the area of high performance reconfigurable computing (HPRC). This book provides an overview of architectures, tools and applications for High-Performance Reconfigurable Computing (HPRC). FPGAs offer very high I/O bandwidth and fine-grained, custom and flexible parallelism and with the ever-increasing computational needs coupled with the frequency/power wall, the increasing maturity and capabilities of FPGAs, and the advent of multicore processors which has caused the acceptance of parallel computational models. The Part on architectures will introduce different FPGA-based HPC platforms: attached co-processor HPRC architectures such as the CHRECs Novo-G and EPCCs Maxwell systems; tightly coupled HRPC architectures, e.g. the Convey hybrid-core computer; reconfigurably networked HPRC architectures, e.g. the QPACE system, and standalone HPRC architectures such as EPFLs CONFETTI system. The Part on Tools will focus on high-level programming approaches for HPRC, with chapters on C-to-Gate tools (such as Impulse-C, AutoESL, Handel-C, MORA-C++); Graphical tools (MATLAB-Simulink, NI LabVIEW); Domain-specific languages, languages for heterogeneous computing(for example OpenCL, Microsofts Kiwi and Alchemy projects). The part on Applications will present case from several application domains where HPRC has been used successfully, such as Bioinformatics and Computational Biology; Financial Computing; Stencil computations; Information retrieval; Lattice QCD; Astrophysics simulations; Weather and climate modeling.

Search system requirements of patent analysts

Patent search tasks are difficult and challenging, often requiring expert patent analysts to spend hours, even days, sourcing relevant information. To aid them in this process, analysts use Information Retrieval systems and tools to cope with their retrieval tasks. With the growing interest in patent search, it is important to determine their requirements and expectations of the tools and systems that they employ. In this poster, we report a subset of the findings of a survey of patent analysts conducted to elicit their search requirements.

Monolithic integration of a spot size transformer with a planar buried heterostructure InGaAsP/InP-laser using the shadow masked growth technique

We present a vertically tapered InGaAsP/InP planar buried heterostructure (PBB) laser for low loss coupling to single-mode fibers. To achieve the vertical tapering we make use of the shadow masked growth technique. Tapered lasers with beam divergences of 15/spl deg/ in both lateral and transverse directions were realized. In comparison with untapered lasers, the coupling losses to cleaved single-mode fibers could be reduced by 4.8 dB down to 5.8 dB.<<ETX>>

III-V semiconductor waveguiding devices using adiabatic tapers

Abstract In the past few years much effort has been put into the fabrication and optimization of III–V semiconductor waveguiding devices with integrated adiabatic mode size converters (tapers). By integrating a taper with a waveguide device, one wants to reduce the coupling losses and the packaging cost of OEICs in future optical communication systems. This paper gives an overview of different taper designs, their performance and the technological approaches used in realizing such tapered devices.

MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.

A multiexit recirculating optical packet buffer

We propose a new type of recirculating buffer, the multiexit buffer (MEB), for use in asynchronous optical packet switches with statistical multiplexing, operating at speeds of 40-100 Gb/s. We demonstrate that the use of this type of buffer dramatically reduces the packet loss for a given buffer depth, thus reducing the buffer depth requirements and the overall cost of the optical packet switching. Physical layer simulation results show that it is possible to build this type of buffer with currently available active components. A hybrid optoelectronic control system is proposed, which allows control of the MEB with a minimum number of active components.

FPGA-accelerated Information Retrieval: High-efficiency document filtering

Power consumption in data centres is a growing issue as the cost of the power for computation and cooling has become dominant. An emerging challenge is the development of ldquoenvironmentally friendlyrdquo systems. In this paper we present a novel application of FPGAs for the acceleration of information retrieval algorithms, specifically, filtering streams/collections of documents against topic profiles. Our results show that FPGA acceleration can result in speed-ups of up to a factor 20 for large profiles.

Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node

An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching.