Wlodek M. Zuberek

Cluster tools with chamber revisiting-modeling and analysis using timed Petri nets

Timed Petri nets are formal models of discrete concurrent systems. Since the durations of all activities are included in the model descriptions, many performance characteristics can be derived from such models. In the case of cluster tools, net models represent the flow of wafers through the chambers of the tool as well as consecutive actions performed by the robotic transporter. Steady-state performance of cluster tools with chamber revisiting is investigated in this paper. A systematic development of detailed tool schedules, based on a general behavioral description of the tool, is proposed and is used to derive the corresponding Petri net models. Symbolic performance characteristics of the modeled tools are obtained by using place invariants, without exhaustive reachability analysis. Simple examples presented in the paper can be easily extended in many ways.

Performance Modeling of Multithreaded Distributed Memory Architectures

In multithreaded distributed memory architectures, long—latency memory operations and synchronization delays are tolerated by suspending the execution of the current thread and switching to another thread, which is executed concurrently with the long—latency operation of the suspended thread. Timed Petri nets are used to model several multithreaded architectures at the instruction and thread levels. Model evaluation results are presented to illustrate the influence of different model parameters on the performance of the system.

Hierarchical analysis of manufacturing systems using Petri nets

Hierarchical analysis of manufacturing systems is performed in a top-down manner in which a general, approximate model is used to capture the main effects of component interconnections, while more detailed models of components provide the detailed information needed for the derivation of performance characteristics of the entire system. For Petri net models, this approach corresponds to stepwise refinements of models. Structural analysis, based on place invariants combined with simple net transformations, is used to obtain performance characteristics of the modeled systems.

Timed Petri net models of cluster tools

Timed Petri nets are used as models of cluster tools, representing not only the concurrent activities of different chambers, but also the durations of these activities. Structural analysis, based on net invariants, provides basic performance measures, such as throughput and cycle time. The results are obtained in symbolic form, so many specific alternatives can easily be compared without repeated analyses of the models.

Performance limitations of block-multithreaded distributed-memory systems

The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results.

Siphon-Based Verification of Component Compatibility

In component-based systems, two interacting components are compatible if any sequence of services requested by one component can be provided by the other. This concept of compatibility can easily be extended to a set of interacting components. Checking the compatibility of interacting components is essential for any dependable software system. Recently, an approach to verification of component compatibility has been proposed in which the behavior of individual components (at component interfaces) was modeled by labeled Petri nets. Moreover, the composition of interacting components was designed in such a way that all component incompatibilities were manifested by deadlocks in the composed model. Consequently, the verification of component compatibility is performed by deadlock analysis of the composed model. One of techniques for deadlock analysis is based on net structures called siphons. Siphon-based verification of component compatibility is the subject of this paper.

Performance analysis of enhanced fine-grain multithreaded distributed-memory systems

In fine-grain multithreading, the thread changes in each processor cycle, consecutive instructions are thus issued from different threads, and no data dependencies stall the pipeline. Enhanced fine-grain multithreading maintains a number of additional threads which are used to replace an active thread when it initiates a long-latency operation. Performance improvements due to enhanced multithreading are studied by analyzing a timed Petri net model of a fine-grain multithreaded architecture at the instruction execution level.

Petri net modeling and performance analysis of cluster tools with chamber revisiting

Timed Petri nets are convenient models of cluster tools as they represent the flow of wafers through the chambers of the tool as well as consecutive actions performed by the robotic transporter. Since the durations of all activities are also represented in such model, performance characteristics can be derived for steady-state as well as for transient behaviors. Steady-state performance of tools with chamber revisiting is investigated in this paper. A general description of cluster tools is proposed for systematic derivation of schedules, and a Petri net model is automatically derived from this description. The performance of the modeled system is derived by using place invariants, without exhaustive reachability analysis.

Optimisation de circuits non linéaires et caractérisation de modèles de composants : association de la méthode du recuit simulé et du simulateur électrique Spice-pac

RésuméLe problème de l’optimisation des performances d’un circuit consiste à déterminer des valeurs acceptables pour les paramètres du circuit (résistances, geometries de transistors⋯) vérifiant au mieux des critères de fonctionnement imposés (temps de montée, largeur de bande fréquentielle⋯). Un problème analogue est celui de la détermination effective des paramètres de composants électroniques : transistors BJT, MOS, SOS, SOI, etc⋯ Ces tâches se ramènent à des problèmes d’optimisation mul-tidimensionnelle non linéaire et/ou multicritère : on doit alors minimiser des fonctions objectifs à n variables dans un domaine hyperrectangulaire avec éventuellement des contraintes d’égalité et/ou d’inégalité. Les auteurs proposent un algorithme efficace, fondé sur l’application de la méthode du « recuit simulé» à un certain nombre de sous-problèmes à p variables, avec p «n, Les fonctions objectifs sont évaluées à l’aide du simulateur électrique modulaire Spice-pac, contrôlé par l’algorithme d’optimisation. La démonstration de l’efficacité du partitionnement en sous-problèmes est détaillée; des exemples numériques montrent l’importance des gains de temps de calcul réalisés.AbstractThe circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistors geometries⋯) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, ⋯). A similar problem deals with efficient transistor parameter determination : BJT, MOS, SOS, SOI, through model fitting to experimental data. This task is equivalent to a multidimensional and/or multiobjective optimization problem : n-variables functions have to be minimized in an hyperrectangular domain; equality and/or inequality constraints can be eventually specified. We propose an efficient algorithm, based on the application of simulated annealing to a certain number of p-variables subproblems, with p « n. Objective functions are computed through the modular Spice-pac simulator, which is controlled by the optimization algorithm. The efficiency of large n-problem splitting into smaller p-subproblems is proved; examples of significant computer time reductions are given.

Deadlock Detection in Distributed Systems Using the IMDS Formalism and Petri Nets

Integrated Model of Distributed Systems (IMDS) is a formalism which expresses duality of message passing and resource sharing and which highlights locality, autonomy of distributed elements as well as asynchrony of actions and communication. Combined with model checking, IMDS allows to verify numerous properties of modeled systems. It also provides insights into the behavior of model components (servers and agents) in the form of server view and agent view of the system. IMDS is used in the Dedan verification environment which can detect several types of deadlocks, including communication deadlocks (in the server view) and resource deadlocks (in the agent view). The paper also outlines a mapping of IMDS models into behaviorally equivalent Petri nets, opening the way for many analysis techniques developed for Petri nets to be used for analysis of IMDS models. In particular, structural (siphon-based) methods for deadlock analysis in Petri nets can be used for deadlock detection in IMDS models.