Wolf-Dietrich Moeller

Design and test of an integrated cryptochip

A self-testing cryptographic coprocessing chip that provides high security for any data protected through its use is described. The design philosophy and chip architecture are examined. Detailed design and test methods and solutions are given, and it is explained why the chips design interacts well in networks and with secure hard disks.<<ETX>>

The peripheral processor pp4, a highly regular VLSI processor

The architecture of an experimental 8/16-bit peripheral processor is described. The chip was fabricated in a 2-μm NMOS technology with two metal layers. There are about 300 000 transistors on a chip area of 105 mm2. The average time for a read-modify-write instruction is 200 ns. A highly modular and regular design style and some automatically generated layouts resulted in a short design time.

A Highly Regular Peripheral Processor

The architecture of an experimental 8/16-bit peripheral processor is described. The chip was fabricated in a 2-μm NMOS technology with two metal layer. There are about 300 000 transistors on a chip area of 105 mm2. The average time for a read-modify-write instruction is 200 ns. A highly modular and regular design style and some automatically generated layouts resulted in a short design time.