Wolfgang Kuebart

High sensitivity InP-based monolithically integrated pin-HEMT receiver-OEIC's for 10 Gb/s

InP-based pin-HEMT receiver-OEICs with different circuit layouts for bit rates up to 10 Gb/s are simulated, realized and characterized. The circuits under investigation are a high impedance amplifier, a common-gate circuit, and a transimpedance-cascode circuit. The high frequency behavior of all circuits is compared by means of on-wafer characterization. All circuits show a bandwidth of more than 5 GHz, the transimpedance circuit has the highest responsivity (12.9 dB A/W) and a very low average noise current of 11.5 pA//spl radic/(Hz) when assembled in a module. The receiver sensitivity of the transimpedance circuit in the module is measured to be as high as -19.2 dBm. >

900 MHz pulse-width-modulated class-s power amplifier with improved linearity

The following paper presents a novel 900MHz pulse-width-modulated current-mode class-S power amplifier. The conversion from an analog to a digital signal, which can be handled by the subsequent switch-mode-stage, is implemented using a fast pulse-width-modulator. The complete class-S amplifier is characterized using clipped WCDMA signals with 5MHz and 80MHz bandwidth, respectively. For the 5MHz signal, the measured spectrum at the amplifiers output shows good EVM of < 12% (approx. 1.5% degradation assumed for class-S PA) and also meets the 3GPP ACLR requirements within 9dB input power range. The capability to support large signal bandwidths is demonstrated, using an 80MHz WCDMA signal, thus meeting the expectations on class-S amplifier for the first time with respect to signal bandwidth.

De-embedding of on-wafer lightwave measurements performed on a monolithic 10 Gb/s InP receiver-oeic

Small-and large-signal measurements on 10 Gb/s monolithic receiver-OEICs of straight forward termination type consisting of InGaAs/InP pin-photodiodes and InAIAs/InGaAs/InP HEMTs are presented. On-wafer characterization of both, isolated devices and OEICs is perforrned using deembedding procedures, which allow for comparison of theoretical and experimental performance.

On-wafer characterization, modelling, and optimization of InP-based HEMTs, PIN-photodiodes and monolithic receiver-OEICs for fiber-optic communication

The authors present results achieved with receiver OEICs (optoelectronic integrated circuits) consisting of InGaAs PIN-photodiodes and InAlAs/InGaAs HEMTs (high electron mobility transistors) grown by low-pressure MOVPE (metalorganic vapor phase epitaxy) on semi-insulating InP substrates. Both devices were realized on the same wafer. A 3-dB bandwidth of 1.6 GHz and an open eye at 3.0 Gb/s NRZ modulation of the monolithically integrated photoreceiver were obtained by on-wafer characterization.<<ETX>>

Optimization of InAlAs/InGaAs heterostructure field effect transistors for an application in optoelectronic receivers

The authors investigate the influence of the layer sequence on transconductance, leakage current, gate-source capacitance, and current gain cut-off frequency and the optimization of InAlAs/InGaAs HEMTs (high electron mobility transistors) for application in optoelectronic receivers. A medium sheet concentration range around 3.0 to 3.5*10/sup 12/ cm/sup -2/ seems to be a good compromise between high-frequency behavior, system sensitivity, and technical aspects for 1- mu m gate length HEMTs. In that range one observes no strong dependence of the leakage current, transit frequency, and gate-source capacitance on the carrier sheet concentration. Further lowering of the doping level and/or a simultaneous increase in doping layer thickness is problematic since the gate to channel distance has to be increased and the contribution of the doping layer to the 2-D electron gas (2DEG) becomes less effective. On the other hand the processing of a wafer with lower doping levels is less critical with respect to the gate recess control. The thermal stability of these layers will be improved also.<<ETX>>

Experimental Comparison of Three Different Circuit Concepts for a Monolithic 10 Gb/s InP-Based Receiver-OEIC

Different circuit concepts for an InP-based 10 Gb/s monolithic front-end receiver-OEIC consisting of an InGaAs/InP pin-photodiode and InAlAs/InGaAs/InP-HEMTs are compared using on-wafer measurements. Small-signal and noise current measurements have been perforied on simple straightforward high impedance OEICs with two different terminations, gate-circuits with a source follower, and transimpedance-cascode circuits to characterise bandwidth, gain or responsivity, electrical output matching, and noise current. The latter reveal a medium input noise current of 13.5 pA/frU¿Hz for the transimpedance circuit, which is the lowest value ever reported for a monolithic 10 Gb/s-receiver-OEIC.